iC-MN 25-BIT NONIUS ENCODER
WITH 3-CH. SAMPLING 13-BIT Sin/D INTERPOLATION
Rev D1, Page 50/59
PRESET FUNCTION
The preset function sets the output position data to a Figure 26; see Figure 27 for multiturn synchronization
predefined position value and is initiated by a high flank operating mode.
at pin PRES or by calling the SOFT_PRES command
(writing 0x02 to the command register, see Table 70).
If an external EEPROM is available the preset values
are read in from the preset registers. A preset value of
zero is otherwise assumed. The current position is de-
termined. Correction factors for the output (OFFS_ST,
OFFS_MT) are calculated and stored in the internal
RAM. With an EEPROM available the entire contents
of the RAM are written to said EEPROM, thus storing
the OFFS_ST and OFFS_MT data.
In the PRES_MT register the multiturn preset values
are always justified to the right with the LSB (starting
at address 0x55, bit 0).
OFFS_MT
Addr. 0x37; bit 7:0
Addr. 0x36; bit 7:0
Addr. 0x35; bit 7:0
0x000
. . .
Multiturn output offset
0xFFF
Note: Command SOFT_PRES blocks iC-MN’s internal
RAM for accesses over a certain time.
Table 96: Position offset for MT data output
For the output the OFFS_ST and OFFS_MT values are
subtracted from the internal synchronized result with
each conversion (Note: In MODE_ST = 0x05-0x07 and
0x0D the sensor data is designated faulty after the first
readout. The readout data is equivalent to the correc-
tion factor.)
PRES_MT
Addr. 0x57; bit 7:0
Addr. 0x56; bit 7:0
Addr. 0x55; bit 7:0
0x000
. . .
Preset register multiturn (EEPROM only)
0xFFF
OFFS_ST
Addr. 0x34; bit 6:0
Addr. 0x33; bit 7:0
Addr. 0x32; bit 7:0
Addr. 0x31; bit 7:0
Addr. 0x30; bit 7:0
Table 97: Preset value for MT data output
up to 12 bit period-information
UBL_S+UBL_N
up to 13 bit master-information
UBL_M
0x00000
. . .
physical
resolution:
MSB
period
LSB
period
MSB
master
LSB
master
Singleturn output offset
0x7FFFF
PRES_ST
register:
MSB
ST_DW
LSB
ST_DW
0
0
0
0
0
0
0
0
Table 94: Position offset for ST data output
ADR 0x54
bit 6
ADR 0x53
bit 3
ADR 0x53
bit 2
ADR 0x51
bit 6
datalength defined by DL_ST
PRES_ST
Addr. 0x54; bit 6:0
Addr. 0x53; bit 7:0
Addr. 0x52; bit 7:0
Addr. 0x51; bit 7:0
Addr. 0x50; bit 7:0
Figure 26: PRES_ST with nonius synchronization
mode
up to 39 bit preset-information MSB left aligned
datalength defined by DL_ST
0x00000
. . .
Preset register singleturn (EEPROM only, see text)
0x7FFFF
PRES_ST
register:
MSB
ST_DW
LSB
ST_DW
0
0
0
Table 95: Preset value for ST data output
ADR 0x54
bit 6
ADR 0x50
bit 0
The position of the preset value for the singleturn data
word (ST_DW) in preset register PRES_ST varies de-
pending on the converter mode (MODE_ST see Table
42). For nonius synchronization operating mode see
Figure 27: PRES_ST with multiturn synchronization
mode
ICHAUS [ IC-HAUS GMBH ]
