iC-MN 25-BIT NONIUS ENCODER
WITH 3-CH. SAMPLING 13-BIT Sin/D INTERPOLATION
Rev D1, Page 53/59
iC-MN internal
address-space visible via BiSS
linear address-
(CFG_E2P > 000)
space divided into n
banks of size 64
bank n-1
byte
(e.g. CFG_E2P > 101; n=32)
bank 3
bank 2
bank 1
ADR
ADR
bank 0
0x00
0x00
0x3F
0x40
0x7F
0x80
0x3F
0x40
BANKSEL
EDSBANK
profile ID
selects
0xBF
0xC0
serial number
SLAVE-registers
STATUS
0xFF
BiSS-ID
0x7F
Figure 29: Principle of bank-wise memory addressing
PROT_E2P(1:0)
Range
Addr. 0x43; bit 1:0
Register access can be restricted via PROT_E2P (see
Table 100). PROT_E2P = 10 selects safety level 2, a
shipping mode with limited access. Shipping 2 can be
set back to level 1 (shipping 1), for which purpose the
content of address 0x43 must be written anew.
RPL*
RP0
RP1
CONF
r/w
EDS
r/w
USER
r/w
STATUS n/a
r/w for others
r/w
r/w
RP2
Note
n/a
r only
r/w
PROT_E2P(1:0)
Addr. 0x43; bit 1:0
* Register Protection Level
Code
Mode
Access Limitation
(see Figure 30 and 31)
00
Configuration Mode,
free access
RP0
RP1
RP2
RP2
Table 101: Register Read/Write Protection Levels
(n/a: iC-MN refuses access to those regis-
ter addresses.)
01
Configuration Mode,
limited access
10
Shipping Mode 1,
reset to RP1 is possible
Figure 30 shows the static memory area and Figure 31
the area which can be altered by BANKSEL. The BiSS
register access limitations which are generated by pa-
rameter PROT_E2P are marked ”R/W” for read/write
access and ”R” for read only. The original site of data
returned by access to the BiSS register is designated
11
Shipping Mode 2,
reset is not possible
Table 100: Register Access Control
Sections CONF, EDS and USER are protected at dif- by ”RAM” for iC-MN’s internal RAM, by ”E2P” for the
ferent levels in shipping mode for read and write ac- EEPROM and by ”INT” for those of iC-MN’s internal
cess.
registers which cannot be preloaded on startup.
ICHAUS [ IC-HAUS GMBH ]
