iC-MN 25-BIT NONIUS ENCODER
WITH 3-CH. SAMPLING 13-BIT Sin/D INTERPOLATION
Rev D1, Page 52/59
EEPROM INTERFACE
CFG_E2P
Adr 0x40; Bit 2:0
Banks per area
(64 bytes each)
CONF EDS USER EEPROM, Typ
The serial EEPROM interface consists of the two pins
SCL and SDA and enables read and write access to a
serial EEPROM (such as a 24C02 with 128 bytes, 5 V
type with a 3.3 V function). The data in the EEPROM
is secured by a CRC to the addresses 0x4E and 0x4F.
Code
For SSI applications:
000*
001
Bytes
128
256
2
3
-
1
-
-
1 kbit, C01 up
2 kbit, C02 up
For BiSS applications with EDS:
Application Hints
010
011
100
101
110
111
Notes
512
3
3
3
3
3
3
4
4
12
4
12
24
1
9
1
25
17
5
4 kbit, C04 up
8 kbit, C08 up
8 kbit, C08 up
16 kbit, C016 up
16 kbit, C016 up
16 kbit, C016 up
To protect the EEPROM against a reversed power sup-
ply voltage it can be connected to the integrated supply
switch (pins VDDA and GNDA). The EEPROM speci-
fications and absolute maximum ratings should com-
ply to the pin voltages of VDDA, SCL and SDA during
startup and operation. A protective circuit may be ad-
visable depending on the EEPROM model.
1024
1024
2048
2048
2048
*) direct addressing mode
Table 99: Configuration of external memory
Direct Addressing
The registers can be accessed via the I/O interface
and direct addressing (for CFG_E2P = 000). In ac-
cordance with the BiSS protocol the number of bytes
addressed is restricted to 128. Accessing addresses
0x00 to 0x4F reads or writes to iC-MN’s internal RAM
register. The data from this special address area can
only be transmitted to the EEPROM by the command
WRITE_CONF.
For EEPROM selection the following minimal require-
ments must be fulfilled: (e. g. Atmel AT24C01B, 128x8)
• Operation from 3.3 V to 5 V, I2C-Interface
• Minimal 1024 bit, 128x8
The registers for addresses 0x50 to 0x70, 0x78 to
0x7B and 0x7D to 0x7F are in the EEPROM and can
be accessed byte-wise by a BiSS register access for
read or write.
CRC_E2P(1:0)
CRC_E2P(9:2)
Addr. 0x4F; bit 7:6
Addr. 0x4E; bit 7:0
Code
0x000
. . .
Description
CRC formed by CRC polynomial 0x409
The addresses missing in the above are located in iC-
MN: the status register from 0x75 to 0x77 (read only),
the MN_CMD register at 0x77 (write only), and the I/O
interface parameters CID_SCD and TOS at address
0x7C. The latter has no access limitations and can
always be read and written to (content is mirrored to
0x4C).
0x3FF
Table 98: EEPROM Data Check Sum
Memory Map And Register Access
Depending on the EEPROM size different bank assign-
ments can be configured using CFG_E2P. There are
three areas, placed one after the other, which are des-
ignated for this purpose in the memory:
Bank-Wise Addressing
iC-MN also supports bank-wise addressing (for
CFG_E2P = 000) according to the BiSS Interface C
Protocol Description. In this mode of configuration iC-
MN divides the internal address sections into banks of
64 bytes each. The address sections visible via the I/O
interface recognizes a ”dynamic” section (addresses
0x00 to 0x3F) and a ”static” section which is perma-
nently visible (addresses 0x40 to 0x7F). The static ad-
dress section is always independent of the bank cur-
rently selected. Figure 29 illustrates how the banks
selected by BANKSEL are addressed.
1. CONF: iC-MN configuration data
2. EDS : Electronic Data Sheet
3. USER: OEM data, free user area
ICHAUS [ IC-HAUS GMBH ]
