iC-MN 25-BIT NONIUS ENCODER
WITH 3-CH. SAMPLING 13-BIT Sin/D INTERPOLATION
Rev D1, Page 36/59
I/O INTERFACE
TOS
Code
00
Addr. 0x4C; bit 1:0
Protocol
Timeout tout
typ. 16 µs
Internal clock counts
iC-MN can transmit position data according to the SSI
protocol where both data length and error messag-
ing are configurable. The selected mode of opera-
tion for sine-to-digital conversion can limit the permissi-
ble SSI clock frequency (see Operating Conditions on
page 15). The highest possible SSI clock frequency
of 4 MHz is permissible for converter modes with an
immediate data output.
31-32
15-16
3-4
01
typ. 8 µs
10
typ. 2 µs
11
typ. 1 µs
1-2
4
fosc
Notes
One clock count is equal to
(see Char. A01)
Table 50: Timeout
Figure 15: Example of SSI line signals
DL_ST
Addr. 0x3E; bit 4:0
Output Data Length
Code
0x00
...
Bit count
For singleturn data lengths (DL_ST) which are less
than 13 bits the SSI data word is zero filled. The op-
tional error bit is always the final bit of the data word.
8 bit plus zeroes (+1 error bit)*
...
0x05
...
13 bit (+1 error bit)*
...
If enabled by M2S, multiturn data is always transmitted
upfront the singleturn data. The format option Gray or
binary code covers the MT and ST data word in its en-
tirety; filled in zeros and the error bit remain untouched.
0x11
25 bit (+1 error bit)*
Bit counts listed below are valid only for multiturn
synchronization mode (s.P. 30 ff.)
0x12
...
26 bit (+1 error bit)*
...
The output bit count is determined by parameters
DL_ST, M2S and ESSI:
0x19
0x1A
Notes
33 bit (+1 error bit)*
39 bit (+1 error bit)*
*) When enabled by ESSI = 1
max(13, DL_ST+ESSI) + MT bits
Table 51: ST Data length
Example: DL_ST = 0 (≡8 Bit); ESSI = 1.
Result: 8 bits of data + 4 zeros + 1 error bit are trans-
mitted = 13 bits of data.
M2S
Code
00
Addr. 0x3F; bit 2:1
Function
no output
01
MT data output of lowest 4 bits
MT data output of lowest 8 bits
Complete output, MT bit count following DL_MT
10
11
Table 52: MT Data output
ICHAUS [ IC-HAUS GMBH ]
