iC-MN 25-BIT NONIUS ENCODER
WITH 3-CH. SAMPLING 13-BIT Sin/D INTERPOLATION
Rev D1, Page 15/59
OPERATING REQUIREMENTS: I/O Interface
Operating conditions: VDD = 5 V ±10 %, Ta = -40...95(110) °C,
IBP calibrated for fosc = 8 MHz, reference point GNDA (GND for digital I/O pins), unless otherwise stated
Item Symbol
No.
Parameter
Conditions
Unit
Min.
Max.
SSI Protocol
I001 TMAS
I002 tMASh
I003 tMASl
I004 tcycle
Permissible Clock Period
tout selected in accordance to Table 50
250
25
2x tout
tout
ns
ns
ns
µs
Clock Signal Hi Level Duration
Clock Signal Lo Level Duration
25
tout
Permissible Cycle Time:
MODE_ST = 0x05...0x07,
11.25
Example for 19-bit ST data from
3-track nonius calculation
UBL_M = 13 bit, UBL_N + SBL_N = 7 bit,
UBL_S + SBL_S = 7 bit
BiSS C Protocol (NBISS = 0x0)
I005 TMAS
I006 tMASh
I007 tMASl
I008 tbusy
Permissible Clock Period
tout selected in accordance to Table 58
100
25
ns
ns
ns
µs
Clock Signal Hi Level Duration
Clock Signal Lo Level Duration
Minimum Data Output Delay
tout
25
MODE_ST = 0x05...0x0B, 0x0D...0x0F,
2x TMAS
MA lo→hi until SLO lo→hi
I009 tbusy
I010 tbusy
I011 tbusy
Maximum Data Output Delay:
Example for 19-bit ST data from
3-track nonius calculation
MODE_ST = 0x00...0x02, fclk(MA) = 10 MHz,
UBL_x and SBL_x see I004
5.3
10
14
µs
µs
µs
Maximum Data Output Delay:
Example for 19-bit ST data from
3-track nonius calculation
MODE_ST = 0x03...0x04, fclk(MA) = 10 MHz,
UBL_x and SBL_x see I004
Maximum Data Output Delay:
Example for 39-bit ST data from
3-track interpolation without
synchronization
MODE_ST = 0x0C, fclk(MA) = 10 MHz,
UBL_M 13 bit, UBL_N 13 bit, UBL_S 13 bit
I012 tcycle
Permissible Cycle Time:
Example for 19-bit ST data from
3-track nonius calculation
MODE_ST = 0x05...0x07,
UBL_x and SBL_x see I004
11.25
µs
Figure 1: I/O Interface timing with SSI protocol
Figure 2: I/O Interface timing with BiSS C protocol
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