iC-MN 25-BIT NONIUS ENCODER
WITH 3-CH. SAMPLING 13-BIT Sin/D INTERPOLATION
Rev D1, Page 12/59
ELECTRICAL CHARACTERISTICS
Operating conditions: VDD = VACO = 5 V ±10 %, Tj = -40...125 °C,
IBP calibrated to 200 µA, reference point GNDA (GND for digital I/O pins), unless otherwise stated
Item Symbol
No.
Parameter
Conditions
Unit
Min.
Typ.
Max.
I/O Interface: RS442 Line Driver Outputs SLO, NSLO
E01
Vs()hi
Saturation Voltage hi
Vs() = VDD − V();
DSC(1:0) = 00, I() = -1.2 mA
DSC(1:0) = 01, I() = -4 mA
DSC(1:0) = 10, I() = -20 mA
DSC(1:0) = 11, I() = -50 mA
200
200
400
900
mV
mV
mV
mV
E02
E03
Vs()lo
Isc()hi
Saturation Voltage lo
Short-circuit Current hi
DSC(1:0) = 00, I() = 1.2 mA
DSC(1:0) = 01, I() = 4 mA
DSC(1:0) = 10, I() = 20 mA
DSC(1:0) = 11, I() = 50 mA
200
200
400
900
mV
mV
mV
mV
V() = 0 V;
DSC(1:0) = 00
DSC(1:0) = 01
DSC(1:0) = 10
DSC(1:0) = 11
-3
-10
-45
-120
-1.2
-4
-20
-50
mA
mA
mA
mA
E04
Isc()lo
Short-circuit Current lo
V() = VDD
DSC(1:0) = 00
DSC(1:0) = 01
DSC(1:0) = 10
DSC(1:0) = 11
1.2
4
20
50
3
10
45
120
mA
mA
mA
mA
E05 Ilk()tri
Tristate Leakage Current
Rise Time hi
DTRI(1:0) = 11
-10
10
µA
E06
tr()
RL = 100 Ω to GND, DSC(1:0) = 11;
DSR(1:0) = 00
DSR(1:0) = 01
DSR(1:0) = 10
DSR(1:0) = 11
10
22
60
30
40
140
350
ns
ns
ns
ns
250
E07
tf()
Fall Time lo
RL = 100 Ω to VDD, DSC(1:0) = 11;
DSR(1:0) = 00
5
22
60
250
15
40
140
350
ns
ns
ns
ns
DSR(1:0) = 01
DSR(1:0) = 10
DSR(1:0) = 11
E08 Ilk()
Residual Current with Reverse
Polarity
-100
100
µA
I/O Interface: RS442 Line Receiver MA, NMA
F01 Vin()
F02 Rin()
F03 Vhys()
F04 Vt()hi
F05 Vt()lo
Permissible Input Voltage
Input Resistance
-7
15
50
12
25
200
2
V
kΩ
mV
V
MA vs. GND, NMA vs. GND
Vhys() = ( V(MA) - V(NMA) ) / 2
20
Differential Input Hysteresis
Input Threshold Voltage hi at MA pin NMA open
Input Threshold Voltage lo at MA pin NMA open
800
mV
MHz
F06
fclk()
Permissible Clock Frequency:
SSI protocol
MODE_ST = 0x05 to 0x0B, 0x0D to 0x0F
4
F07 fclk()
Permissible Clock Frequency:
BiSS protocol
NBISS = 0
10
50
MHz
ns
F08 tp(MA-
SLO)
Propagation Delay:
MA edge vs. SLO output
RL(SLO/NSLO) = 120 Ω
10
F09
Processing Time Singlecycle
Data (delay of start bit)
Nonius modes:
tbusy_s
MODE_ST = 0x00 to 0x02
MODE_ST = 0x03 to 0x04, 2 track
MODE_ST = 0x03 to 0x04, 3 track
MODE_ST = 0x05 to 0x0B
MT modes:
tcnv *1
tcnv *2
tcnv *3
0
µs
µs
µs
µs
MODE_ST = 0x0C, 3 track
MODE_ST = 0x0D to 0x0F
tcnv *3
0
µs
µs
F10 tbusy_r
F11 tidle
Processing Time Register Ac-
cess (delay of start bit)
with read access to EEPROM
2
2
ms
Interface Blocking Time
powering up without EEPROM
ms
ICHAUS [ IC-HAUS GMBH ]
