iC-MH8
12 BIT ANGULAR HALL ENCODER
Rev A0.9, Page 6/25
ELECTRICAL CHARACTERISTICS
Operating conditions:
VPA, VPD = 5 V ±10 %, VNA=VND, Tj = -40...125 °C, IBM adjusted to 200 µA , 4 mm NdFeB magnet, unless otherwise noted
Item Symbol
No.
Parameter
Conditions
Unit
Min.
Typ.
Max.
407 Vosr
Reference voltage offset com-
pensation
475
500
525
mV
Clock Generation
501 f()sys
System Clock
Bias Current adjusted
Bias Current adjusted
0.85
13.5
1.0
16
1.2
18
MHz
MHz
502 f()sdc
Sinus/Digital-Converter Clock
Sin/Digital Converter
601 RESsdc
Sinus/Digital-Converter Resolu-
12
Bit
tion
602 AAabs
Absolute Angular Accuracy
Relative Angular Accuracy
Vpp() = 4 V, adjusted
-0.35
0.35
Deg
%
603
604
AArel
f()ab
with reference to an output periode at A, B.
CFGRES=0x2, ENF=1, PRM=0, HCLH=1,
GAING=0x0, Vpp(SIN/COS) = 4 Vpp.
see Fig. 17
± 10
Output frequency at A, B
CFGMTD = 0x0, CFGRES=0x0
CFGMTD = 0x7, CFGRES=0x0
2.0
0.25
MHz
MHz
Serial Interface, Digital Outputs MA, SLO, SLI
701 Vs(SLO)hi Saturation Voltage High
V(SLO) = V(VPD) − V(),
0.4
0.4
V
I(SLO) = 4 mA
702 Vs(SLO)lo Saturation Voltage Low
703 Isc(SLO)hi Short-Circuit Current High
704 Isc(SLO)lo Short-Circuit Current Low
I(SLO) = 4 mA to VND
V(SLO) = V(VND), 25°C
V(SLO) = V(VPD), 25°C
CL = 50 pF
V
mA
mA
ns
-90
-50
50
80
60
60
2
705 tr(SLO)
706 tf(SLO)
707 Vt()hi
Rise Time SLO
Fall Time SLO
CL = 50 pF
ns
Threshold Voltage High: MA, SLI
Threshold Voltage Low: MA, SLI
Threshold Hysteresis: MA, SLI
Pull-Down Current: MA, SLI
V
708 Vt()lo
0.8
140
6
V
709 Vt()hys
710 Ipd()
250
30
mV
µA
µA
MHz
V() = 0...VPD − 1 V
60
-6
711 Ipu(MA)
712 f(MA)
-60
-30
10
Zapping and Test
801 Vt()hi
Threshold Voltage High VZAP,
PTE
with reference to VND
with reference to VND
Vt()hys = Vt()hi − Vt()lo
2
V
V
802 Vt()lo
Threshold Voltage Low VZAP,
PTE
0.8
803 Vt()hys
Hysteresis
140
0.7
250
7.0
mV
V
804 Vt()nozap Threshold Voltage Nozap VZAP V() = V(VZAP) − V(VPA), V(VPA) = 5 V ±5 %,
at chip temperature 27 °C
805 Vt()zap
Threshold Voltage Zap VZAP
V() = V(VZAP) − V(VPA), V(VPA) = 5 V ±5 %,
1.2
V
at chip temperature 27 °C
806 V()zap
807 V()zpd
808 V()uzpd
Zapping voltage
PROG = ’1’
6.9
7.1
2
V
V
Diode voltage, zapped
Diode voltage, unzapped
3
V
809 Rpd()VZAP Pull-Down Resistor at VZAP
30
55
kΩ
NERR Output
901 Vt()hi
902 Vs()lo
903 Vt()lo
904 Vt()hys
905 Ipu()
Input Threshold Voltage High
Saturation Voltage Low
Input Threshold Voltage Low
Input Hysteresis
with reference to VND
I() = 4 mA , with reference to VND
with reference to VND
Vt()hys = Vt()hi − Vt()lo
V(NERR) = 0...VPD − 1 V
V(NERR) = V(VPD), Tj = 25°C
CL = 50 pF
2
V
V
0.4
0.8
140
-800
V
250
-300
50
mV
µA
mA
ns
Pull-up Current Source
Short circuit current Lo
Decay time
-80
80
60
906 Isc()lo
907 tf()hilo
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