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IC-MDTSSOP20 参数 Datasheet PDF下载

IC-MDTSSOP20图片预览
型号: IC-MDTSSOP20
PDF下载: 下载PDF文件 查看货源
内容描述: 编码器接收器/计数器, SPI和BiSS接口 [ENCODER RECEIVER/COUNTER WITH SPI AND BiSS]
分类和应用: 计数器编码器
文件页数/大小: 23 页 / 451 K
品牌: ICHAUS [ IC-HAUS GMBH ]
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iC-MD RS-422 QUADRATURE  
ENCODER RECEIVER/COUNTER WITH SPI AND BiSS  
Rev A1, Page 11/23  
48 BIT COUNTER  
iC-MD has a 48 bit counter configurable as from one EXCH = 0 and INVZ = 0. All other configurations are  
up to three counters with bit lengths from 16 to 48 bit. also possible.  
Table 16 shows all the possible counters configuration.  
CFGZ  
Code  
00  
Addr. 0x01; bit (4:3)  
Function:  
00  
The counter configuration is given by the registers  
CNTCFG as shown in table 16. If it is configured with  
more than one counter, the input stage must be set to  
TTL (table 12).  
Z active: when A = 1 B = 1  
Z active: when A = 1 B = 0  
Z active: when A = 0 B = 1  
Z active: when A = 0 B = 0  
01  
10  
11  
CNTCFG  
Code  
000  
Addr. 0x00; bit (2:0)  
Counter Configuration  
000  
Table 17: Index Signal Configuration  
1x24 bit counter  
2x24 bit counter  
1x48 bit counter  
1x32 bit counter  
1x32 bit + 1x16 bit counter  
1x16 bit counter  
2x16 bit counter  
3x16 bit counter  
001  
It can also be deactivated the clearing of counter by  
the index signal with the configuration bit CBZ ( table  
18 ).  
010  
100  
101  
011  
The CBZ configuration is only applicable after the sec-  
ond index pulse after power-on or the activation of  
ZCEN (table 23), because after it, the iC-MD will reset  
the counter value by the firsts two index pulse, inde-  
pendently of the CBZ configuration, in order to have  
the AB Counter value referenced to the second index  
pulse. By default, CBZ is set to 0, also the counters  
are not reset to 0 by the index signal. But the firsts two  
Index pulse always reset the counters.  
110  
111  
Table 16: Counter Length  
The 48 bit register of the AB counter is also used as  
"SPI data channel" for data exchanging between SPI  
and BiSS interface, for that purpose the bit CH0SEL  
(table 45) must be set to 1. When CH0SEL = 1, the  
counting function for all the counters is deactivated.  
CBZ  
Code  
x1  
Addr. 0x01; bit (6:5)  
Function  
00  
CNT0 cleared by Z0 signal  
CNT1 cleared by Z1 signal  
1x  
Index Signal (Z)  
In default operation configuration, the index signal (Z)  
is active when A = B = 1, as shown in table 17 with  
Table 18: Clear by Z  
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