iC-MD RS-422 QUADRATURE
ENCODER RECEIVER/COUNTER WITH SPI AND BiSS
Rev A1, Page 12/23
24 BIT REFERENCE COUNTER
An aditional 24 bit counter is integrated in order to load Since the internal counter for REF and UPD is 24 bit
the REF and UPD registers. The value of this internal long, the maximum number of edges that can be eval-
counter can not be read, it can only be read the values uated (loaded in UPD and REF) between two index
of REF and UPD registers. The reference counter is signal goes from -223 (negative counting direction) to
activated by default after power-on and reset with ev- 223-1 (positive counting direction).
ery index signal (it is not affected by the configuration
bit CFGZ, table 17).
REF REGISTER
After the start up (Power on), the iC-MD counts the dex signals. The AB counter is then set to 0 with the
number of edges between the first two different index second index signal. The counter value is then refer-
signals (Z) in the register REF. This function is always enced to the position of the second Z signal, and the
activated by the following situations:
number of edges between the first two index signals
stored in REF.
- after power-on.
- by activating the zero codification function via instruc- After the second index signal, the status bit RVAL (ta-
tion byte (table 23).
ble 31) is set and remains at this value until the next
power on, the activation of the zero codification func-
The process runs as following: the "reference counter" tion or until the reseting of the counter 0.
is set to zero with the first index signal, and the second
index signal (must be different of the first one) loads The following diagrams show the reference position ac-
the register REF with the value of "reference counter". quisition process also called as zero codification func-
It is the distance between the first and the second in- tion.
Figure 2: Zero-Codification: REF and UPD registers after activation of Zero Codification function
Figure 3: Zero-Codification: reference position acquisition