iC-MD RS-422 QUADRATURE
ENCODER RECEIVER/COUNTER WITH SPI AND BiSS
Rev A1, Page 10/23
RS-422, LVDS, TTL RECEIVERS
LVDS
Code
0
Addr. 0x03; bit (7)
0
The input stage for the incremental signals ABZ is con-
figurable as single-ended TTL and differential (RS-422
or LVDS). Differential inputs are possible only for one
counter configuration. If two or more counters are con-
figured, it must be used one of the TTL inputs configu-
ration shown in table 11.
Function
differential RS-422 inputs
differential LVDS inputs
condition: TTL=0
1
Notes
Table 13: LVDS/RS-422 Inputs
Counters A0 B0 Z0 A1 B1 Z1 A2 B2
The configuration bit EXCH exchanges the input A and
the input B of the counters. The default counting di-
rection is positive in clockwise (CW) direction (A edge
take place before B edge). But it is also possible to
change the counting direction with the register EXCH.
See table 14.
1xTTL AP AN BP
2xTTL AP AN BP BN CP CN
3xTTL AP AN BP BN
-
-
-
-
-
-
-
-
-
CP CN
Table 11: TTL Input Counters Configuration
EXCH
Code
xx1
Addr. 0x00; bit (5:3)
Function
000
Note that the three counters configuration don’t imple-
ment any Zero signal. It has only A and B input signals.
Register bits TTL and LVDS set the configuration of the
quadrature input signals.
exchange AB CNT0 (CCW positive)
exchange AB CNT1 (CCW positive)
exchange AB CNT2 (CCW positive)
x1x
1xx
Table 14: Exchange AB Inputs
TTL
Code
0
Addr. 0x01; bit (7)
Function
0
The index (Z) signal can be inverted as shown in table
15 with the register bits INVZ(1:0).
differential inputs
TTL inputs
1
INVZ
Code
x1
Addr. 0x00; bit (7:6)
Function
00
Table 12: TTL Inputs
invert Z CNT0 (Z=0 active)
invert Z CNT1 (Z=0 active)
1x
It is possible to configure the differential input stage of
iC-MD in two different modes; differential RS-422 and
differential LVDS. See table 13.
Table 15: Invert Z Signal
ICHAUS [ IC-HAUS GMBH ]
