iC-MD RS-422 QUADRATURE
ENCODER RECEIVER/COUNTER WITH SPI AND BiSS
Rev A1, Page 7/23
CONFIGURATION PARAMETERS
Read/Write Registers
Read-Only Registers
Status
Configuration
AB
counter values
INVZ(1:0)
EXCH(2:0)
CNTCFG(2:0) counter configuration
TTL
CBZ(1:0)
CFGZ(1:0)
TPCFG(1:0)
PRIOR
invert Z signal
exchange inputs AB
NERR
NWARN
TP1
error bit (low active)
warning bit (low active)
touch-probe 1 register
TTL/differential inputs
clear counter by zero
zero signal configuration
TPI configuration
SPI/BiSS communication priority
error/warning mask
NTPVAL
touch-probe valid (low active)
NABERR AB counter error (low active)
TP2
REF
UPD
touch-probe 2 register
reference register
update register
MASK(9:0)
NUPDVAL update register valid (low active)
NMASK(1:0) error/warning not mask
LVDS
LVDS/RS-422 differential inputs
Table 7: Counter Registers
CH2SEL
ENCH2
CH1SEL
ENCH1
CH0SEL
NENCH0
BiSS channel 2 select
BiSS channel 2 enable
BiSS channel 1 select
BiSS channel 1 enable
BiSS channel 0 select
BiSS channel 0 not enable
Error
ABERRx AB signals error in counter x
EXTERR external error
Table 8: Error Registers
Table 5: Register description
Warning
OVFx
overflow in counter x
Write-Only Registers
ZEROx
PDWN
RVAL
signals zero value in counter x
power-down reset
REF value valid
Instructions
ACT1
ACT0
TP
set value of ACT1 pin
set value of ACT0 pin
latch TP1 and TP2
UPDVAL
OVFREF
TPVAL
update register up to date
overflow in REF counter
new touch-probe value available
ZCEN
enable zero codification
EXTWARN external warning
ABRES2 reset AB counter 2
ABRES1 reset AB counter 1
ABRES0 reset AB counter 0
COMCOL communication collision
TPS
actual TPI pin status
SSI enabled
ENSSI
Table 6: Instruction Byte
Table 9: Warning Registers
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