iC-JRX
µP INTERFACE WITH 2×4 24V HIGH-SIDE DRIVERS
Rev A1, Page 5/23
Control Word 1 (I/O filters)
Add.: 10
reset entry: 00h
higher nibble
lower nibble
Bit
7
6
5
4
3
2
-
1
0
Name
BYPH
-
FH1
FH0
BYPL
FL1
FL0
higher nibble
Bit 7
0
I/O filters active
(r)
BYPH
1
Bypass for I/O filters: the I/O signals are reprocessed in their unfiltered state.
Bit 5..4
FH1..0
FH1
FH0
Filter times
0
0
1
1
0
1
0
1
14.5 × tc(CLK)
± 1 × tc(CLK)
896.5 × tc(CLK)
3584.5 × tc(CLK)
7168.5 × tc(CLK)
± 64 × tc(CLK)
± 256 × tc(CLK)
± 512 × tc(CLK)
lower nibble
Bit 3
0
I/O filters active
Bypass for I/O filters: the I/O signals are reprocessed in their unfiltered state.
(r)
(r)
BYPL
1
Bit 1..0
FL1..0
FL1
FL0
Filter times
0
0
1
1
0
1
0
1
14.5 × tc(CLK)
± 1 × tc(CLK)
896.5 × tc(CLK)
3584.5 × tc(CLK)
7168.5 × tc(CLK)
± 64 × tc(CLK)
± 256 × tc(CLK)
± 512 × tc(CLK)
'-'
'xx'h Indicates hexadecimal data for logic states. ‘x’ indicates binary data
(r) Status after a reset
Free memory location without a function. Status after a reset is ‘0’
ICHAUS [ IC-HAUS GMBH ]
