iC-JRX
µP INTERFACE WITH 2×4 24V HIGH-SIDE DRIVERS
Rev A1, Page 3/23
PACKAGES PLCC44 to JEDEC Standard
PIN CONFIGURATION PLCC44
(top view)
PIN FUNCTIONS PLCC44
No. Name Fct. Description
No. Name Fct. Description
1
2
3
4
5
6
7
8
9
CSN
WRN
RDN
BLFQ
CLK
INTN
RESN
D1
I
Chip Select, active low
Write Enable, active low
Read Enable, active low
Clock Flash Mode
23 PGND
24 IO3
25 VB23
26 IO2
27 IO1
28 VB01
29 IO0
30 VCCA
31 POE
32 n.c.
33 n.c.
34 VCCD
35 D6
Ground (ESD protection circuitry)
I
B
I/O Stage 3
I
Power Supply Driver Stage 2+3
I/O Stage 2
I
B
B
I
Clock Filter and PWM Function
Interrupt Message, active low
Reset, active low
I/O Stage 1
O
I
Power Supply Driver Stage 0+1
I/O Stage 0
B
I
B
B
B
B
Data Bus Bit 1
+5 V Supply Voltage (analog section)
Power Output Enable
D3
Data Bus Bit 3
10 D5
Data Bus Bit 5
11 D7
Data Bus Bit 7
12 GNDD
13 n.c.
14 n.c.
15 TEST
16 GNDA
17 IO7
18 VB67
19 IO6
20 IO5
21 VB45
22 IO4
Ground (digital section)
+5 V Supply Voltage (digital section)
Data Bus Bit 6
B
B
B
B
I
36 D4
Data Bus Bit 4
B
B
Test Pin
37 D2
Data Bus Bit 2
Ground (analog section)
I/O Stage 7
38 D0
Data Bus Bit 0
39 A0
Address Bus Bit 0
Address Bus Bit 1
Address Bus Bit 2
Address Bus Bit 3
Address Bus Bit 4
Power Supply Driver Stage 6+7
I/O Stage 6
40 A1
I
B
B
41 A2
I
I/O Stage 5
42 A3
I
Power Supply Driver Stage 4+5
I/O Stage 4
43 A4
I
B
44 n.c.
Functions: I = Input, O = Output, B = bidirectional
External wiring VCCA, VCCD to +5 V and GNDA, GNDD, PGND to 0 V required.
ICHAUS [ IC-HAUS GMBH ]
