iC-JRX
µP INTERFACE WITH 2×4 24V HIGH-SIDE DRIVERS
Rev A1, Page 7/23
Control Word 3 (flash pulse settings)
Add.: 12
reset entry: 00h
higher nibble
lower nibble
Bit
7
6
5
4
3
-
2
-
1
0
Name
NOBLFQ NOCLK
PH1
PH0
PL1
PL0
higher nibble
Bit 7
0
Flash pulse is generated from the external clock signal at BLFQ
Flash Pulse is generated from clock signal CLK
(r)
(r)
NOBLFQ
1
Bit 6
0
1
Operation with the clock signal at CLK (all clock controlled actions are possible)
Operation without the clock signal at CLK (filtering etc. deactivated)
NOCLK
Bit 5..4
PH1..0
Flash frequency for I/O pins 4..7
PH1
PH0
NOBLFQ = 0
NOBLFQ = 1
0
0
1
1
0
1
0
1
f(BLFQ)
f(CLK) / 219
f(CLK) / 220
f(CLK) / 221
f(CLK) / 223
f(BLFQ) / 2
f(BLFQ) / 4
f(BLFQ) / 16
(r)
(r)
lower nibble
Bit 1..0
Flash frequency for I/O pins 0..3
PL1..0
PL1
PL0
NOBLFQ = 0
NOBLFQ = 1
0
0
1
1
0
1
0
1
f(BLFQ)
f(CLK) / 219
f(CLK) / 220
f(CLK) / 221
f(CLK) / 223
f(BLFQ) / 2
f(BLFQ) / 4
f(BLFQ) / 16
Control Word 4 (filter settings for overcurrent message)
Add.: 13
reset entry: 00h
Bit
7
6
-
5
-
4
3
2
-
1
-
0
Name
EOI
SCFH
BYPSCF
SCFL
Bit 7
EOI
0
1
No effect
(r)
"DELETE"s the interrupt message (change-of-input message; interrupt status register, overcurrent
message), accepts successive interrupts from the pipeline, deletes the message at INTN when the pipeline
is empty;
Bit automatically resets to '0'.
Bit 4
0
1
Overcurrent message with 2.3ms filtering (higher nibble)
Overcurrent message with 4.6ms Filtering (higher nibble)
(r)
SCFH
Gives the filter times with the maximum clock frequency permitted at CLK, i.e. 1.25 MHz:
2.3ms from (2689.5 ± 192)× t(CLK) and
4.6ms from (5378.5 ± 384) × t(CLK) respectively
Bit 3
0
1
Filters for the overcurrent message are active
(r)
(r)
BYPSCF
Bypass for the filters: overcurrent messages are reprocessed in their unfiltered state
Bit 0
0
1
Overcurrent message with 2.3 ms filtering (lower nibble)
Overcurrent message with 4.6 ms filtering (lower nibble)
SCFL
ICHAUS [ IC-HAUS GMBH ]
