Si4430/31/32-B1
The configurable preamble detector is used to improve the reliability of the sync-word detection. The sync-word
detector is only enabled when a valid preamble is detected, significantly reducing the probability of false detection.
The received signal strength indicator (RSSI) provides a measure of the signal strength received on the tuned
channel. The resolution of the RSSI is 0.5 dB. This high resolution RSSI enables accurate channel power
measurements for clear channel assessment (CCA), carrier sense (CS), and listen before talk (LBT) functionality.
Frequency mistuning caused by crystal inaccuracies can be compensated by enabling the digital automatic
frequency control (AFC) in receive mode.
A comprehensive programmable packet handler including key features of Silicon Labs’ EZMAC is integrated to
create a variety of communication topologies ranging from peer-to-peer networks to mesh networks. The extensive
programmability of the packet header allows for advanced packet filtering which in turn enables a mix of broadcast,
group, and point-to-point communication.
A wireless communication channel can be corrupted by noise and interference, and it is therefore important to
know if the received data is free of errors. A cyclic redundancy check (CRC) is used to detect the presence of
erroneous bits in each packet. A CRC is computed and appended at the end of each transmitted packet and
verified by the receiver to confirm that no errors have occurred. The packet handler and CRC can significantly
reduce the load on the system microcontroller allowing for a simpler and cheaper microcontroller.
The digital modem includes the TX modulator which converts the TX data bits into the corresponding stream of
digital modulation values to be summed with the fractional input to the sigma-delta modulator. This modulation
approach results in highly accurate resolution of the frequency deviation. A Gaussian filter is implemented to
support GFSK, considerably reducing the energy in the adjacent channels. The default bandwidth-time product
(BT) is 0.5 for all programmed data rates, but it may not be adjusted to other values.
5.6. Synthesizer
An integrated Sigma Delta (ΣΔ) Fractional-N PLL synthesizer capable of operating from 240–960 MHz is provided
on-chip. The Si4431/32 and Si4430 cover different frequencies. This section discusses the frequency range
covered by all EZRadioPRO devices. Using a ΣΔ synthesizer has many advantages; it provides flexibility in
choosing data rate, deviation, channel frequency, and channel spacing. The transmit modulation is applied directly
to the loop in the digital domain through the fractional divider which results in very precise accuracy and control
over the transmit deviation.
Depending on the part, the PLL and - modulator scheme is designed to support any desired frequency and
channel spacing in the range from 240–960 MHz with a frequency resolution of 156.25 Hz (Low band) or 312.5 Hz
(High band). The transmit data rate can be programmed between 0.123–256 kbps, and the frequency deviation
can be programmed between ±1–320 kHz. These parameters may be adjusted via registers as shown in "3.5.
Frequency Control" on page 25.
TX
Selectable
Divider
Fref = 10 M
PFD
CP
LPF
RX
VCO
N
TX
Modulation
Delta-
Sigma
Figure 16. PLL Synthesizer Block Diagram
The reference frequency to the PLL is 10 MHz. The PLL utilizes a differential L-C VCO, with integrated on-chip
inductors. The output of the VCO is followed by a configurable divider which will divide down the signal to the
desired output frequency band. The modulus of the variable divide-by-N divider stage is controlled dynamically by
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IBM [ IBM ]
