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SI4432 参数 Datasheet PDF下载

SI4432图片预览
型号: SI4432
PDF下载: 下载PDF文件 查看货源
内容描述: [中辉电子商行主营业务: 主营: 直插八脚  光耦 DIP  SOP 二三极管 场效应等,可接受配单,敬请垂询! 网址1:http://www.zhonghui-su.com 网址2:http://www.zh-su.com 英文网站01:http://www.iceach.com/ic/contact.asp?id=1270_117569 英文网站02:http://www.zhonghui-su.com/default_en.asp 销售一部;苏小姐 苏先生 销售二部;赵先生 苏小姐 电话: 0755-33060853 非值班手机: 13480103950 13421310323 OICQ:506518680,529439314, 296200415 MSN: zh-su@hotmail.com 传真: 0755-33060853 EMail: 506518680@qq.com 公司柜台: 深圳市福田区华强北赛格高科德电子市场1楼12260柜台]
分类和应用: 电子手机电话
文件页数/大小: 74 页 / 875 K
品牌: IBM [ IBM ]
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Si4430/31/32-B1  
6. Data Handling and Packet Handler  
The internal modem is designed to operate with a packet including a 10101... preamble structure. To configure the  
modem to operate with packet formats without a preamble or other legacy packet structures contact customer  
support.  
6.1. RX and TX FIFOs  
Two 64 byte FIFOs are integrated into the chip, one for RX and one for TX, as shown in Figure 17. "Register 7Fh.  
FIFO Access" is used to access both FIFOs. A burst write, as described in "3.1. Serial Peripheral Interface (SPI)"  
on page 18, to address 7Fh will write data to the TX FIFO. A burst read from address 7Fh will read data from the  
RX FIFO.  
TX FIFO  
RX FIFO  
RX FIFO Almost Full  
Threshold  
TX FIFO Almost Full  
Threshold  
TX FIFO Almost Empty  
Threshold  
Figure 17. FIFO Thresholds  
The TX FIFO has two programmable thresholds. An interrupt event occurs when the data in the TX FIFO reaches  
these thresholds. The first threshold is the FIFO almost full threshold, txafthr[5:0]. The value in this register  
corresponds to the desired threshold value in number of bytes. When the data being filled into the TX FIFO crosses  
this threshold limit, an interrupt to the microcontroller is generated so the chip can enter TX mode to transmit the  
contents of the TX FIFO. The second threshold for TX is the FIFO almost empty threshold, txaethr[5:0]. When the  
data being shifted out of the TX FIFO drops below the almost empty threshold an interrupt will be generated. The  
microcontroller will need to switch out of TX mode or fill more data into the TX FIFO. The transceiver can be  
configured so that when the TX FIFO is empty it will automatically exit the TX state and return to one of the low  
power states. When TX is initiated, it will transmit the number of bytes programmed into the packet length field  
(Reg 3Eh). When the packet ends, the chip will return to the state specified in register 07h. For example, if 08h is  
written to address 07h then the chip will return to the STANDBY state. If 09h is written then the chip will return to  
the READY state.  
Rev 1.0  
41  
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