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SI4432 参数 Datasheet PDF下载

SI4432图片预览
型号: SI4432
PDF下载: 下载PDF文件 查看货源
内容描述: [中辉电子商行主营业务: 主营: 直插八脚  光耦 DIP  SOP 二三极管 场效应等,可接受配单,敬请垂询! 网址1:http://www.zhonghui-su.com 网址2:http://www.zh-su.com 英文网站01:http://www.iceach.com/ic/contact.asp?id=1270_117569 英文网站02:http://www.zhonghui-su.com/default_en.asp 销售一部;苏小姐 苏先生 销售二部;赵先生 苏小姐 电话: 0755-33060853 非值班手机: 13480103950 13421310323 OICQ:506518680,529439314, 296200415 MSN: zh-su@hotmail.com 传真: 0755-33060853 EMail: 506518680@qq.com 公司柜台: 深圳市福田区华强北赛格高科德电子市场1楼12260柜台]
分类和应用: 电子手机电话
文件页数/大小: 74 页 / 875 K
品牌: IBM [ IBM ]
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Si4430/31/32-B1  
Only FSK and OOK modulation types are valid in TX Direct Asynchronous Mode; GFSK modulation is not available  
in asynchronous mode. This is because the RFIC does not have knowledge of the supplied data rate, and thus  
cannot determine the appropriate Gaussian lowpass filter function to apply to the incoming data.  
One advantage of this mode that it saves a microcontroller pin because no TX Clock output function is required.  
The primary disadvantage of this mode is the increase in occupied spectral bandwidth with FSK (as compared to  
GFSK).  
nIRQ  
nSEL  
SCLK  
VDD_RF  
TX  
SCK  
Direct synchronous modulation. Full  
control over the standard SPI & using  
interrupt. Bitrate clock and modulation  
via GPIO’s.  
SDI  
MOSI  
MISO  
SDO  
RXp  
RXn  
NC  
Matching  
C  
VDD_DIG  
NC  
GPIO configuration  
MOD  
GP0 : power-on-reset (default)  
GP1 : TX DATA clock output  
GP2 : TX DATA input  
DATACLK  
nRES  
DataCLK  
MOD(Data)  
Figure 13. Direct Synchronous Mode Example  
nIRQ  
nSEL  
SCLK  
SCK  
Direct asynchronous FSK modulation.  
Modulation data via GPIO2, no data  
clock needed in this mode.  
VDD_RF  
TX  
SDI  
SDO  
MOSI  
MISO  
RXp  
RXn  
NC  
Matching  
C  
VDD_DIG  
NC  
GPIO configuration  
GP0 : power-on-reset (default)  
GP1: not utilized  
MOD  
GP2 : TX DATA input  
nRES  
MOD(Data)  
Figure 14. Direct Asynchronous Mode Example  
4.2.2.3. Direct Mode using SPI or nIRQ Pins  
In certain applications it may be desirable to minimize the connections to the microcontroller or to preserve the  
GPIOs for other uses. For these cases it is possible to use the SPI pins and nIRQ as the modulation clock and  
data. The SDO pin can be configured to be the data clock by programming trclk = 10. If the nSEL pin is LOW then  
the function of the pin will be SPI data output. If the pin is high and trclk[1:0] is 10 then during RX and TX modes  
the data clock will be available on the SDO pin. If trclk[1:0] is set to 11 and no interrupts are enabled in registers 05  
or 06h, then the nIRQ pin can also be used as the TX/RX data clock.  
The SDI pin can be configured to be the data source in both RX and TX modes if dtmod[1:0] = 01. In a similar  
fashion, if nSEL is LOW the pin will function as SPI data-in. If nSEL is HIGH then in TX mode it will be the data to  
Rev 1.0  
35  
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