IBMN612404GT3B
IBMN612804GT3B
Preliminary
128Mb Double Data Rate Synchronous DRAM
DDR SDRAM Device Labeling Guide
P/N code: aaabbccddefggh - jjj
Meaning
Applies to
Definition
Digit
aaa
Manufacturer
All Devices IBM
Product family/quality
designator
bb
All Devices 06 = Industry Standard premium DDR SDRAM
All Devices 25 = 256Mb, 13 row (4 bank devices only)
cc
Density & Addressing
40 = x4
Planar
dd
Data Width
Devices
80 = x8
4 = 4 logical banks, does not support QFC\ function
All Devices
Number of logical banks
and QFC\ support
e
f
5 = 4 logical banks, includes QFC\ function
Power (all devices sup-
port self refresh mode)
All Devices G = Standard Power, SSTL_2, V =V =2.5V
dd
ddq
1st Digit:
T = TSOP
gg
h
Package Type
All Devices
2nd Digit:
3 = 400 mil package width
Die Revision Code
All Devices B = 1st shrink
Part Speed Designator:
1st and 2nd Digit: (2nd digit is dropped if representing x.0 ns)
7 = Intended for 143MHz @CL=2.5
75= Intended for 133MHz @ CL=2.5
This is specified at the
maximum clock fre-
quency of the device.
However, the same
device will support
8 = Intended for 125MHz @ CL=2.5
jjj
All Devices
3rd Digit (represents CL/t
/t for the specific clock cycle
RCD RP
defined by the 1st and 2nd digits above):
N: CL=2.5, t = 3, t =3
smaller CAS latencies
for lower frequencies.
RCD
RP
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
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