IBMN612404GT3B
IBMN612804GT3B
Preliminary
128Mb Double Data Rate Synchronous DRAM
Block Diagram (16Mb x 8)
CKEn
CK
QFC
generator
QFC
(Optional)
DRVR
CK
CSn
WE
CAS
RAS
Bank3
Bank2
Bank1
Clk
DLL
Mode
Registers
12
4096
Bank0
Memory
Array
12
Data
1
(4096 x 512 x 16)
8
8
8
16
Sense Amplifiers
DQS
Generator
DQ0-DQ7,
DM
COLo
Mask
DQS
Input
Register
1
I/O Gating
DM Mask Logic
16
2
DQS
1
A0-A11,
BA0, BA1
Write
14
1
8
FIFO
1
1
&
16
2
16
512
(x8)
2
Drivers
8
8
8
8
clk
clk
Column
Decoder
in
out
Data
9
COLo
Clk
Column-Address
Counter/Latch
10
COLo
1
1
Note: This Functional Block Diagram is intended to facilitate user understanding of the operation of
the device; it does not represent an actual circuit implementation.
Note: DM is a unidirectional signal (input only), but is internally loaded to match the load of the bidi-
rectional DQ and DQS signals.
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
06K0566.F39350B
1/01
Page 7 of 79
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