IBMN612404GT3B
IBMN612804GT3B
128Mb Double Data Rate Synchronous DRAM
Preliminary
Pin Configuration - 128Mb DDR SDRAM (x4 / x8)
VDD
VSS
VSS
NC
VDD
DQ0
VDDQ
NC
1
2
3
4
5
66
65
64
63
62
NC
VDDQ
NC
DQ7
VSSQ
NC
VSSQ
NC
DQ0
DQ6
DQ3
DQ1
VSSQ
NC
VDDQ
NC
VDDQ
NC
VSSQ
NC
6
61
60
59
58
57
7
NC
DQ5
VSSQ
NC
NC
DQ2
VDDQ
NC
8
VDDQ
NC
VSSQ
NC
9
10
DQ3
DQ1
VSSQ
NC
DQ4
DQ2
11
12
56
55
VSSQ
NC
VDDQ
VDDQ
NC
NC
13
14
15
16
17
18
19
20
54
53
52
51
50
49
48
47
NC
NC
NC
NC
VSSQ
DQS
NC
VSSQ
DQS
NC
VDDQ
NC
VDDQ
NC
NC
VDD
NC
VDD
VREF
VSS
DM*
VREF
VSS
DM*
DNU, QFC+
NC
DNU, QFC+
NC
WE
WE
CK
CK
CK
CK
21
22
23
46
45
44
CAS
CAS
RAS
RAS
CKE
CKE
CS
NC
CS
NC
NC
NC
NC
NC
24
25
43
42
BA0
BA1
BA0
BA1
A11
A9
A11
A9
26
27
41
40
A8
A8
A10/AP
A10/AP
28
29
39
38
A7
A7
A0
A1
A2
A0
A1
A2
A6
A5
A6
A5
30
31
37
36
A3
A3
A4
A4
32
33
35
34
VDD
VSS
VSS
VDD
66-pin Plastic TSOP-II 400mil
16Mb x 8
IBMN62580
32Mb x 4
IBMN62540
Column Address Table
Organization
Column Address
A0-A9, A11
A0-A9
32Mb x 4
16Mb x 8
*DM is internally loaded to match DQ and DQS identically.
+QFC is an optional feature and must be specified via p/n when ordering devices.
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
06K0566.F39350B
1/01
Page 2 of 79
IBM [ IBM ]
