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IBMN612405GT3B-8N 参数 Datasheet PDF下载

IBMN612405GT3B-8N图片预览
型号: IBMN612405GT3B-8N
PDF下载: 下载PDF文件 查看货源
内容描述: [DDR DRAM, 32MX4, 0.8ns, CMOS, PDSO66, 0.400 INCH, PLASTIC, TSOP2-66]
分类和应用: 时钟动态存储器双倍数据速率光电二极管内存集成电路
文件页数/大小: 79 页 / 1280 K
品牌: IBM [ IBM ]
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IBMN612404GT3B  
IBMN612804GT3B  
Preliminary  
128Mb Double Data Rate Synchronous DRAM  
Register Definition  
Mode Register  
The Mode Register is used to define the specific mode of operation of the DDR SDRAM. This definition  
includes the selection of a burst length, a burst type, a CAS latency, and an operating mode. The Mode Reg-  
ister is programmed via the Mode Register Set command (with BA0 = 0 and BA1 = 0) and retains the stored  
information until it is programmed again or the device loses power (except for bit A8, which is self-clearing).  
Mode Register bits A0-A2 specify the burst length, A3 specifies the type of burst (sequential or interleaved),  
A4-A6 specify the CAS latency, and A7-A11 specify the operating mode.  
The Mode Register must be loaded when all banks are idle, and the controller must wait the specified time  
before initiating the subsequent operation. Violating either of these requirements results in unspecified opera-  
tion.  
Burst Length  
Read and write accesses to the DDR SDRAM are burst oriented, with the burst length being programmable.  
The burst length determines the maximum number of column locations that can be accessed for a given  
Read or Write command. Burst lengths of 2, 4, or 8 locations are available for both the sequential and the  
interleaved burst types.  
Reserved states should not be used, as unknown operation or incompatibility with future versions may result.  
When a Read or Write command is issued, a block of columns equal to the burst length is effectively  
selected. All accesses for that burst take place within this block, meaning that the burst wraps within the block  
if a boundary is reached. The block is uniquely selected by A1-Ai when the burst length is set to two, by A -Ai  
2
when the burst length is set to four and by A -Ai when the burst length is set to eight (where Ai is the most  
3
significant column address bit for a given configuration). The remaining (least significant) address bit(s) is  
(are) used to select the starting location within the block. The programmed burst length applies to both Read  
and Write bursts.  
©IBM Corporation. All rights reserved.  
Use is further subject to the provisions at the end of this document.  
06K0566.F39350B  
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