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IBMB3N16644JCB-75AT 参数 Datasheet PDF下载

IBMB3N16644JCB-75AT图片预览
型号: IBMB3N16644JCB-75AT
PDF下载: 下载PDF文件 查看货源
内容描述: [Synchronous DRAM Module, 16MX64, 5.4ns, CMOS, DIMM-168]
分类和应用: 时钟动态存储器内存集成电路
文件页数/大小: 18 页 / 315 K
品牌: IBM [ IBM ]
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Preliminary
IBMB3N16644JCB
IBMB3N16734JCB
16M x 64/72 One-Bank Unbuffered SDRAM Module
DC Output Load Circuit
3.3 V
1200Ω
Output
870Ω
50pF
V
OH
(DC) = 2.4V, I
OH
= -2mA
V
OL
(DC) = 0.4V, I
OL
= 2mA
Input/Output Characteristics
Symbol
(T
A
= 0 to +70°C, V
DD
= 3.3V
±
0.3V)
x64
Parameter
Min.
RAS, CAS, WE, CKE0,
A0-A9, A10/AP, A11, BA0, BA1
CK0
CK2
S0
-8
-4
-4
-4
-4
-1
-1
-1
0
-10
-10
-1
0
-10
2.4
-
Max.
+8
+4
+4
+4
+4
+1
+1
+1
0
+10
+50
+1
0
+10
-
0.4
Min.
-9
-5
-4
-5
-4
-2
-1
-1
-1
-10
-10
-1
-1
-10
2.4
-
Max.
+9
+5
+4
+5
+4
+2
+1
+1
+1
+10
+50
+1
+1
+10
-
0.4
V
1
µA
µA
x72
Units Notes
I
I(L)
Input Leakage Current, any input
(0.0V
V
IN
V
DD
), All Other Pins
Not Under Test = 0V
S2
DQMB1
DQMB0, 2, 3, 4, 5, 6, 7
DQ0 - 63
CB0 - 7
SA0, SA1, SA2, SCL, SDA
WP
I
O(L)
Output Leakage Current
(D
OUT
is disabled, 0.0V
V
OUT
V
DD
)
Output Level (LVTTL)
Output “H” Level Voltage (I
OUT
= -2.0mA)
Output Level (LVTTL)
Output “L” Level Voltage (I
OUT
= +2.0mA)
DQ0 - 63
CB0 - 7
SDA
V
OH
V
OL
1. See DC output load circuit.
75H2785.H42054
11/00
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
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