Preliminary
IBMB3N16644JCB
IBMB3N16734JCB
16M x 64/72 One-Bank Unbuffered SDRAM Module
(Part 2 of 2)
SPD Entry Value
128MB
1.5ns
0.8ns
1.5ns
0.8ns
Undefined
67ns
Undefined
1.2
Checksum Data
IBM
MM
16M x 64,
-75A
16M x 72,
-75A
Serial PD Data Entry
(Hexadecimal)
20
15
08
15
08
00
43
00
12
cc
A400000000000000
3, 4
Notes
Serial Presence Detect
Byte #
31
32
33
34
35
Module Bank Density
Description
Address and Command Setup Time Before Clock
Address and Command Hold Time After Clock
Data Input Setup Time Before Clock
Data Input Hold Time After Clock
36 - 40 Reserved for VCSDRAM
Minimum Bank Cycle Time (t
RC
)
41
42 - 61 Reserved
62
SPD Revision
63
Checksum for bytes 0 - 62
64 - 71 Manufacturers’ JEDEC ID Code
72
Module Manufacturing Location
73 - 90 Module Part Number
91 - 92 Module Revision Code
93 - 94 Module Manufacturing Date
95 - 98 Module Serial Number
99 - 125 Reserved
126
Module Supports this Clock Frequency
127
128 -
255
1.
2.
3.
4.
5.
6.
7.
8.
mm
ASCII ‘B3N16644JCB-75AT’ 42334E31363634344A43
422D373541542020
42334E31363733344A43
ASCII ‘B3N16734JCB-75AT’
422D373541542020
‘B’ plus ASCII blank
4220
Year/Week Code
yyww
Serial Number
Undefined
100 MHz
CK0, CK2, CL2, CL3,
concurrent AP
Undefined
ssssssss
00
64
A7
00
5, 6
Attributes for Clock Frequency defined in byte 126
Open for Customer Use
See the AC output load circuit in the AC Characteristics section below
cc = Checksum Data byte, 00-FF (Hex)
“MM” = Alphanumeric revision code, A-Z, 0-9
mm= ASCII coded revision code byte “MM”
yy = Binary coded decimal year code, 00-99 (Decimal) 00-63 (Hex)
ww = Binary coded decimal week code, 01-52 (Decimal) 01-34 (Hex)
ss = Serial number data byte, 00-FF (Hex)
For PC-100 applications only.
75H2785.H42054
11/00
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 7 of 18
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