IBMB3N16644JCB
IBMB3N16734JCB
Preliminary
16M x 64/72 One-Bank Unbuffered SDRAM Module
AC Characteristics (TA= 0 to +70°C, VDD= 3.3V ± 0.3V)
1. An initial pause of 200µs, with DQMB0-7 and CKE0 held high, is required after power-up. A Precharge All
Banks command must be given followed by a minimum of eight Auto (CBR) Refresh cycles before or after
the Mode Register Set operation.
2. The Transition time is measured between V and V (or between V and V ).
IH
IL
IL
IH
3. In addition to meeting the transition rate specification, the CK0, CK2, and CKE0 signals must transit
between V and V (or between V and V ) in a monotonic manner.
IH
IL
IL
IH
4. AC timing tests have V = 0.8 V and V = 2.0 V with the timing referenced to the 1.40V crossover point.
IL
IH
5. AC measurements assume t =1.2 ns.
T
AC Characteristics Diagrams
t
T
t
CKH
V
IH
1.4V
Clock
Input
t
CKL
V
IL
t
SETUP
Output
t
HOLD
Zo = 50Ω
50pF
1.4V
AC Output Load Circuit
t
OH
t
AC
t
LZ
1.4V
Output
75H2785.H42054
11/00
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Use is further subject to the provisions at the end of this document.
Page 11 of 18
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