IBMB3N16644JCB
IBMB3N16734JCB
16M x 64/72 One-Bank Unbuffered SDRAM Module
Preliminary
Presence Detect Read and Write Cycle
Symbol
Parameter
Min.
Max.
100
100
3.5
Units
Notes
f
SCL Clock Frequency
kHZ
ns
µs
µs
µs
µs
µs
µs
µs
ns
µs
ns
µs
ns
ms
SCL
T
Noise Suppression Time Constant at SCL, SDA Inputs
SCL Low to SDA Data Out Valid
Time the Bus Must Be Free before a New Transmission Can Start
Start Condition Hold Time
I
t
0.3
4.7
4.0
4.7
4.0
4.7
0
AA
t
BUF
t
HD:STA
t
Clock Low Period
LOW
t
Clock High Period
HIGH
t
Start Condition Setup Time (for a Repeated Start Condition)
Data in Hold Time
SU:STA
t
HD:DAT
t
Data in Setup Time
250
SU:DAT
t
SDA and SCL Rise Time
1
r
t
SDA and SCL Fall Time
300
f
t
Stop Condition Setup Time
4.7
SU:STO
t
Data Out Hold Time
300
DH
t
1
Write Cycle Time
15
WR
1. The Write cycle time (t ) is the time from a valid stop condition of a write sequence to the end of the internal Erase/Program
WR
cycle. During the Write cycle, the bus interface circuits are disabled, SDA is allowed to remain high per the bus-level pull-up resis-
tor, and the device does not respond to its slave address.
75H2785.H42054
11/00
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
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