IBM PowerPRS Q-64G
Preliminary
Packet Routing Switch
List of Figures
Figure 2-1. System View of the PowerPRS Q-64G with the PowerPRS C192 ............................................ 15
Figure 2-2. PowerPRS Q-64G Block Diagram ............................................................................................. 16
Figure 2-3. 16 × 16 Subswitch Element Block Diagram ............................................................................... 17
Figure 2-4. 512-Gbps Configuration ............................................................................................................. 22
Figure 2-5. 256-Gbps Configuration ............................................................................................................. 23
Figure 3-1. Packet Format for a 16-Gbps Port ............................................................................................. 28
Figure 3-2. Ingress Idle Packet Format ........................................................................................................ 31
Figure 3-3. Ingress Data Packet and Control Packet Format ....................................................................... 33
Figure 3-4. Ingress Service Packet Format .................................................................................................. 36
Figure 3-5. Egress Idle Packet Format ......................................................................................................... 39
Figure 3-6. Egress Data Packet and Control Packet Format ....................................................................... 44
Figure 3-7. Egress Service Packet Format ................................................................................................... 46
Figure 3-8. Best-Effort Discard Counters and Thresholds ............................................................................ 51
Figure 3-9. Best-Effort Discard Drop Filters ................................................................................................. 52
Figure 6-1. Ingress Speed-Expansion Bus Data Latency ........................................................................... 157
Figure 6-2. Egress Speed-Expansion Bus Data Latency ........................................................................... 157
Figure 7-1. SHI Signal Timing Diagram ...................................................................................................... 166
Figure 7-2. SHI Signal-to-Clock Timing Diagram ....................................................................................... 166
Figure 7-3. SyncOut/SyncIn Signal Timing Diagram .................................................................................. 167
Figure 9-1. Pinout ....................................................................................................................................... 173
Figure 10-1. Internal PLL AVDD and AGND Signals .................................................................................. 187
Figure 11-1. Package Mechanical .............................................................................................................. 189
prsq-64g.01LOF.fm
December 20, 2001
List of Figures
Page 9 of 199
IBM [ IBM ]
