IBM PowerPRS Q-64G
Packet Routing Switch
Preliminary
5.3 Functional Registers ................................................................................................................... 110
5.3.1 Configuration 0 Register ...................................................................................................... 110
5.3.2 Configuration 1 Register ...................................................................................................... 112
5.3.3 Threshold Access Register .................................................................................................. 114
5.3.4 Credit Table Access Register .............................................................................................. 116
5.3.5 Best-Effort Resources Access Register ............................................................................... 118
5.3.6 Status Register .................................................................................................................... 120
5.3.7 Interrupt Mask Register ........................................................................................................ 122
5.3.8 Output Queue Enable Register ............................................................................................ 124
5.3.9 Input Controller Enable Register .......................................................................................... 124
5.3.10 Bitmap Filter Register ........................................................................................................ 125
5.3.11 Color Detection Disable Register ....................................................................................... 125
5.3.12 Expected Color Received Register .................................................................................... 126
5.3.13 Color Command Register .................................................................................................. 127
5.3.14 Bitmap Mapping Register ................................................................................................... 128
5.3.15 Output Queue Status Registers ......................................................................................... 129
5.3.16 Best-Effort Discard Alarm Register .................................................................................... 131
5.3.17 Send Grant Violation Register ........................................................................................... 131
5.3.18 Header Parity Error Register .............................................................................................. 132
5.3.19 Flow Control Violation Register .......................................................................................... 132
5.3.20 Side Communication Channel Input Reporting Registers .................................................. 133
5.4 Control Packet and Service Packet Transmission Registers ................................................. 134
5.4.1 Egress Control Packet and Service Packet Payload Registers ........................................... 134
5.4.2 Egress Control Packet and Service Packet Destination Register ........................................ 135
5.5 Control Packet and Service Packet Reception Registers ....................................................... 136
5.5.1 Ingress Control Packet or Command Service Packet Received Registers .......................... 136
5.5.2 Ingress Control Packet and Service Packet Source Register .............................................. 137
5.5.3 Ingress Control Packet and Service Packet Payload Registers .......................................... 138
5.5.4 Ingress Event Service Packet Received Registers .............................................................. 139
5.5.5 Ingress Event Service Packet Mask Registers .................................................................... 139
5.6 Debug Facilities Registers ......................................................................................................... 140
5.6.1 Debug Bus Select Register .................................................................................................. 140
5.6.2 Send Grant Disable Register ............................................................................................... 142
5.6.3 Force Send Grant Register .................................................................................................. 142
5.6.4 Send Grant Status Registers ............................................................................................... 143
5.6.5 Subswitch Element Occupancy (1) Registers ...................................................................... 144
5.6.6 Subswitch Element Occupancy (2) Registers ...................................................................... 145
5.6.7 Look-Up Table Registers ..................................................................................................... 146
5.6.8 Blue Idle Packet or Data Packet Received Register ............................................................ 147
5.6.9 Red Idle Packet or Data Packet Received Register ............................................................ 147
5.6.10 Miscellaneous Debug Register .......................................................................................... 148
5.6.11 Force Packet Capture Ports Register ................................................................................ 150
5.6.12 Force Packet Capture Header Register ............................................................................. 151
5.6.13 Force Packet Capture Mask Register ................................................................................ 152
5.6.14 Packet Captured Registers ................................................................................................ 152
5.6.15 Unilink Debug Control Register .......................................................................................... 153
5.6.16 Unilink Force Error Register ............................................................................................... 154
Contents
prsq-64g.01TOC.fm
December 20, 2001
Page 6 of 199
IBM [ IBM ]
