IBM PowerPRS Q-64G
Preliminary
Packet Routing Switch
List of Tables
Table 2-1. Multiple-Device Configuration Summary ..................................................................................... 21
Table 3-1. Ingress Idle Packet, Byte H0 ....................................................................................................... 31
Table 3-2. Ingress Idle Packet, Byte H0 Field Descriptions ......................................................................... 31
Table 3-3. Ingress Idle Packet, Bytes H1, H2, SCC, and FC ....................................................................... 32
Table 3-4. Ingress Data Packet and Control Packet, Byte H0 ...................................................................... 33
Table 3-5. Ingress Data Packet and Control Packet, Byte H0 Field Descriptions ........................................ 34
Table 3-6. Ingress Data Packet and Control Packet, Byte H1 in the 256-Gbps Configuration ..................... 35
Table 3-7. Ingress Data Packet and Control Packet, Bytes H1 and H2 in the 512-Gbps Configuration ...... 35
Table 3-8. Ingress Service Packet, Byte H0 ................................................................................................. 36
Table 3-9. Ingress Service Packet, Byte H0 Field Descriptions ................................................................... 36
Table 3-10. Egress Idle Packet, Byte H0 ...................................................................................................... 39
Table 3-11. Egress Idle Packet, Byte H0 Field Descriptions ........................................................................ 40
Table 3-12. Egress Idle Packet, Byte H1 on the High Channel in the 256-Gbps Configuration ................... 41
Table 3-13. Egress Idle Packet, Byte H1 on the High Channel in the 512-Gbps Configuration ................... 41
Table 3-14. Egress Idle Packet, Byte H2 on the High Channel in the 512-Gbps Configuration ................... 42
Table 3-15. Egress Idle Packet, Byte H1 on the Low Channel in the 256-Gbps Configuration .................... 42
Table 3-16. Egress Idle Packet, Bytes H1 and H2 on the Low Channel in the 512-Gbps Configuration ..... 43
Table 3-17. Egress Idle Packet, SCC Byte ................................................................................................... 43
Table 3-18. Egress Idle Packet, FC Byte ..................................................................................................... 43
Table 3-19. Egress Idle Packet, FC Byte Field Descriptions ........................................................................ 44
Table 3-20. Egress Data Packet and Control Packet, H0 Byte .................................................................... 45
Table 3-21. Egress Data Packet and Control Packet, Byte H0 Field Descriptions ....................................... 45
Table 3-22. Egress Service Packet, Byte H0 ............................................................................................... 46
Table 3-23. Egress Service Packet, Byte H0 Field Descriptions .................................................................. 46
Table 3-24. Best-Effort Discard Counters ..................................................................................................... 50
Table 3-25. Flow Control Information Summary ........................................................................................... 54
Table 3-26. Packet Transmission Time ........................................................................................................ 56
Table 3-27. Example of Byte Reordering Using the Look-Up Table ............................................................. 57
Table 3-28. Registers and Bits Used for Switchover Support ...................................................................... 58
Table 3-29. Ingress Data Packet Protection Field ........................................................................................ 58
Table 4-1. SHI OpCode Commands ............................................................................................................. 62
Table 5-1. Register Map ............................................................................................................................... 63
Table 5-2. DebugBusOut[0:15] Pin Information by Debug Bus Select Field Value .................................... 140
Table 6-1. Required Data Latency .............................................................................................................. 158
Table 7-1. Signal Definitions ....................................................................................................................... 163
Table 7-2. Power Signals ........................................................................................................................... 164
Table 7-3. Test Signals ............................................................................................................................... 165
prsq-64g.01LOT.fm
December 20, 2001
List of Tables
Page 11 of 199
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