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    IBM3229P2815 参数 Datasheet PDF下载

    IBM3229P2815图片预览
    型号： IBM3229P2815
    PDF下载： 下载PDF文件 查看货源
    内容描述： [Packet Routing Switch, CMOS, PBGA624, 33 X 33 MM, BGA-624]
    分类和应用： 电信电信集成电路
    文件页数/大小： 199 页 / 1779 K
    品牌： IBM [ IBM ]
     浏览型号IBM3229P2815的Datasheet PDF文件第1页浏览型号IBM3229P2815的Datasheet PDF文件第2页浏览型号IBM3229P2815的Datasheet PDF文件第3页浏览型号IBM3229P2815的Datasheet PDF文件第5页浏览型号IBM3229P2815的Datasheet PDF文件第6页浏览型号IBM3229P2815的Datasheet PDF文件第7页浏览型号IBM3229P2815的Datasheet PDF文件第8页浏览型号IBM3229P2815的Datasheet PDF文件第9页  
    IBM PowerPRS Q-64G
    Packet Routing Switch
    Preliminary
    3.3.6 Flow Control Flywheels for Grants Carried in Egress Packets ..............................................
    3.3.6.1 Extended Output Queue Grant Flywheel ........................................................................
    3.3.6.2 Output Queue Grant Priority Flywheel ............................................................................
    3.3.6.3 Subport Grant Type/Priority Flywheel .............................................................................
    3.3.6.4 Subport Grant Port Flywheel ..........................................................................................
    3.3.7 Egress Idle Packet Format .....................................................................................................
    3.3.8 Egress Data Packet and Control Packet Format ...................................................................
    3.3.9 Egress Service Packet Format ..............................................................................................
    3.4 Ingress Flow Control .....................................................................................................................
    3.4.1 Output Queue Grants .............................................................................................................
    3.4.2 Memory Grants ......................................................................................................................
    3.4.3 Multicast Grants .....................................................................................................................
    3.4.4 Shared Memory Overrun .......................................................................................................
    3.4.5 Flow Control Latency .............................................................................................................
    3.4.6 Best-Effort Discard .................................................................................................................
    3.4.6.1 Best-Effort Discard Counters ..........................................................................................
    3.4.6.2 Best-Effort Discard Thresholds .......................................................................................
    3.4.6.3 Best-Effort Discard Filters ...............................................................................................
    3.5 Egress Flow Control .....................................................................................................................
    3.5.1 Send Grants ...........................................................................................................................
    3.5.2 Send Grant Antistreaming ......................................................................................................
    3.5.3 Credit Table ...........................................................................................................................
    3.6 Subport Flow Control ....................................................................................................................
    3.7 Flow Control Information Summary ............................................................................................
    3.8 Packet Reception ..........................................................................................................................
    3.8.1 Data Packet Reception ..........................................................................................................
    3.8.2 Control and Service Packet Reception ..................................................................................
    3.9 Packet Transmission ....................................................................................................................
    3.9.1 Output Port Servicing .............................................................................................................
    3.9.2 Control and Service Packet Transmission .............................................................................
    3.9.3 Idle Packet Transmission .......................................................................................................
    3.9.4 Look-Up Table .......................................................................................................................
    3.10 Side Communication Channel ...................................................................................................
    3.11 Switchover Support ....................................................................................................................
    3.11.1 Scheduled Switchover Process ...........................................................................................
    3.11.1.1
    Phase 1: Rerouting Traffic to One Switch Plane .....................................................
    3.11.1.2
    Phase 2: Modifying the Load-Balancing Configuration ..........................................
    3.11.1.3
    Phase 3: Resuming Traffic on Both Switch Planes .................................................
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    4. Programming Interface ............................................................................................. 61
    4.1 SHI Instruction Register ...............................................................................................................
    4.2 SHI Instruction Execution .............................................................................................................
    4.3 SHI Parity Checking ......................................................................................................................
    4.4 SHI Parity Generation ...................................................................................................................
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    5. Register Descriptions ............................................................................................... 63
    5.1 SHI Internal Registers ................................................................................................................... 67
    5.1.1 Internal PLL Programming Register ....................................................................................... 67
    5.1.2 Internal PLL Status Register .................................................................................................. 67
    Contents
    prsq-64g.01TOC.fm
    December 20, 2001
    Page 4 of 199

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