IBM PowerPRS Q-64G
Preliminary
Packet Routing Switch
Contents
List of Figures ................................................................................................................. 9
List of Tables ................................................................................................................. 11
1. General Information .................................................................................................. 13
1.1 Features ......................................................................................................................................... 13
1.2 Description .................................................................................................................................... 13
1.3 Ordering Information .................................................................................................................... 14
1.4 Conventions and Notation ........................................................................................................... 14
2. Architecture ............................................................................................................... 15
2.1 System Application ....................................................................................................................... 15
2.2 Internal Structure .......................................................................................................................... 16
2.2.1 Unilink Interface ..................................................................................................................... 17
2.2.2 Shared Memory ..................................................................................................................... 18
2.2.3 Sequencer ............................................................................................................................. 18
2.2.4 Address Managers ................................................................................................................ 18
2.2.5 Input Controllers .................................................................................................................... 19
2.2.6 Output Queue Access Managers .......................................................................................... 19
2.2.7 Output Queues ...................................................................................................................... 19
2.2.8 Output Queue Scheduler and Credit Table ........................................................................... 20
2.2.9 Output Controllers ................................................................................................................. 20
2.3 Multiple-Device Configurations ................................................................................................... 20
2.3.1 512-Gbps Configuration ........................................................................................................ 21
2.3.2 256-Gbps Configuration ........................................................................................................ 21
2.3.3 Master/Slave Synchronization with Multiple Devices ............................................................ 21
2.3.3.1 Sequencers .................................................................................................................... 21
2.3.3.2 Shared Memory Addresses ............................................................................................ 23
3. Functional Description ............................................................................................. 25
3.1 Packet Types ................................................................................................................................. 25
3.1.1 Data Packets ......................................................................................................................... 25
3.1.2 Control Packets ..................................................................................................................... 26
3.1.3 Service Packets ..................................................................................................................... 26
3.1.4 Idle Packets ........................................................................................................................... 26
3.2 Physical Interface and Packet Processing ................................................................................. 26
3.3 Packet Format According to Packet Type .................................................................................. 28
3.3.1 General Packet Format Information ...................................................................................... 28
3.3.1.1 Packet Header ................................................................................................................ 28
3.3.1.2 Flow Control Flywheels .................................................................................................. 29
3.3.2 Flow Control Flywheels for Grants Carried in Ingress Packets ............................................. 29
3.3.2.1 Subport Grant Type/Subport Flywheel ........................................................................... 30
3.3.2.2 Grant Priority Flywheel ................................................................................................... 30
3.3.3 Ingress Idle Packet Format .................................................................................................... 30
3.3.4 Ingress Data Packet and Control Packet Format .................................................................. 32
3.3.5 Ingress Service Packet Format ............................................................................................. 35
prsq-64g.01TOC.fm
December 20, 2001
Contents
Page 3 of 199
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