IBM PowerPRS Q-64G
Preliminary
Packet Routing Switch
Packets are transmitted in equal lengths called logical units (LUs). The number of LUs depends on the device
configuration. The LU bytes of two packets carried over a Unilink are serialized in the following order:
• LU for packet 0, byte 0
• LU for packet 1, byte 0
• LU for packet 0, byte 1
• LU for packet 1, byte 1
This pattern continues through the final two LU bytes, which are serialized as follows:
• LU for packet 0, byte (LU length - 1)
• LU for packet 1, byte (LU length - 1)
Each Unilink differential pair operates at 2.5 Gbps. The Unilink data stream is a single 400-ps bit stream that
carries 8b/10b encoding for link synchronization and supervision.
On the ingress path, the PowerPRS Q-64G physical interface deserializes the Unilink data stream into a
10-bit, 4-ns data stream. The physical interface performs byte alignment and removes the 8b/10b code,
translating the 10-bit stream into an 8-bit stream. It also demultiplexes the 4-ns data stream into two 8-ns
(125 MBps) byte streams, one byte stream for each LU. The two byte streams are carried over separate
buses to the input controller. The high-channel bus carries the LU for packet 0 and the low-channel bus
carries the LU for packet 1. Although the Unilink physical throughput is 2.5 Gbps, the Unilink logical
throughput is only 2 Gbps because the Unilink data stream carries 8b/10b encoding.
On the egress path, this process is reversed. The PowerPRS Q-64G physical interface multiplexes the two
8-ns byte streams into a single 4-ns byte stream, adds 8b/10b encoding, and serializes the data into a single
400-ps bit stream.
In the standard 256-Gbps or 512-Gbps PowerPRS Q-64G configuration, each 16-Gbps port is comprised of
eight Unilinks. Each packet is divided into eight LUs, and each Unilink carries one LU from each packet. The
first LU of a packet is the master, and the other LUs are the slaves. The master LU carries packet header
bytes, which contain packet control information and precede packet payload bytes. Slave LUs carry only pay-
load bytes. The LU length is either 8, 9, or 10 bytes depending on the device configuration.
Figure 3-1 illustrates how the master and slave LUs of two data packets are distributed over the eight Unilinks
that comprise a port. The master Unilink carries the master LUs of both packets. Each slave Unilink carries
one slave LU from each of the two packets.
Because PowerPRS Q-64G data is transmitted with a known clock, only bit phase alignment and packet
delineation must be performed. All eight packet LUs are received or transmitted on all eight Unilink ports
simultaneously. All eight LUs must arrive at the device port input pins within a 4-ns time frame; that is, the
difference between the time the first bit of the first LU arrives at its input pin and the time the first bit of the last
LU arrives at its input pin must be within 4 ns. External software running on the local processor compensates
for any skew between the multiple Unilink ports.
When an input port simultaneously receives two data packets destined for the same output port, the output
queue stores the address of the packet received on the high channel before it stores the address of the
packet received on the low channel because, internally, the packet received on the high channel is consid-
ered to have arrived first. Similarly, when an output port transmits two data packets simultaneously, the
attached device processes the packet carried on the high channel first to ensure correct packet serialization
through the switch. The LUs of successive packets are transported sequentially, with no gap between them.
prsq-64g.01.fm
December 20, 2001
Functional Description
Page 27 of 199
IBM [ IBM ]
