IBM3229P2035
IBM Packet Routing Switch Serial Interface Converter
Advance
4.1.1.35 Common Control Register
The PLL observe bits automatically overwrite the microprocessor writes.
SlotID
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Reset Output Status (Power-on-Reset)
Address in Word Mode
Address in Byte Mode
Access Type
‘0500413F’
x'A0’
x'A0 to A3’
Read/Write
Bits/
Word
Bits/
Bytes
Name
Description
Select Ingress Clock source:
00
01
10
11
Microprocessor
31-30
7-6
UCLK_source_l[1:0]
PE clock used to time the PE interface
External smoothing PLL
Microprocessor clock
Priority Enable controls the cycling process of Output Queue Grant and Shared
Memory Grant information from the switch
00
01
10
11
Enable only Priority 0
29-28
27
5-4
3
NbPriority
Enable Priority 0 and 1 enabled
Enable Priority 0, 1 and 2
Enable Priority 0, 1, 2 and 3 (all four priorities in use)
Unused
Smooth PLL out selection and driver enable
0
The selected switch clock used by the converter is not the one used to drive
an external smoothing PLL. In this case, a clock coming from the PE itself (or
an external oscillator) is used to drive the PE interface rather than the
From_Smooth_PLL_out.
26
2
SMOOTH_select_enb_l
1
The To_Smooth_PLL_In interface line is used to drive the PE interface to sup-
port a smooth switching from one clock plane to the other in case of switch
plane switchover. In that case, the switch and the protocol engines are clock
synchronous.
Switch_X Clock selector:
11
10
01
00
Normal setting: selects Switch Fabric X Clock for Switch X interface
Selects external TEST_CLK oscillator for switch X interface
Selects external MP_CLK oscillator for switch X interface
25-24
1-0
SWX_TC_source_enb_l[1:0]
Selects Force Clock ‘1’ for Switch interface X (may be used for clock miss
detection)
Converter Configuration Table Registers
Page 98 of 154
prssi.02.fm
March 1, 2001
IBM [ IBM ]
