IBM3229P2035
IBM Packet Routing Switch Serial Interface Converter
Advance
4.1.1.36 Interrupt Register Indirection
Unused
Unused
Unused
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Reset Output Status (Power-on-Reset)
Address in Word Mode
Address in Byte Mode
Access Type
All ’0’s
x'A4’
x'A4 to A7’
Read/Write
Bits /
Word
Bits /
Bytes
Name
Description
31-24
7-0
7-0
7-0
7
Unused
Unused
Unused
23-16
15-8
7
YEvent1B1
YEvent1B0
XEvent1B1
XEvent1B0
Event 1 on plane Y byte 1
Event 1 on plane Y byte 0
Event 1 on plane X byte 1
Event 1 on plane X byte 0
Unused
6
6
5
5
4
4
3-2
1
3-2
1
Event2B1
Event2B0
Event 2 byte1
0
0
Event 2 byte 0
Note: The PLL Clock missing bits are not implemented.
Note: The bits in this register are followers of what is occuring in other triggering registers. To clear a bit in
this register, its source must be cleared. For example, if a bit is set in Register 18 (Interrupt Enable _X), Reg-
ister 38 (Event 1 Interrupt Enable _Y), or Register 84 (Event 2 µP Interrupt Enable_X and _Y), the corre-
sponding bit in this register will be set. When the bits in those registers are cleared, the corresponding bit in
this register is cleared.
Converter Configuration Table Registers
Page 100 of 154
prssi.02.fm
March 1, 2001
IBM [ IBM ]
