IBM3229P2035
IBM Packet Routing Switch Serial Interface Converter
Advance
Bits /
Word
Bits /
Bytes
Name
Description
RXDATA vs. RXENB calibration up to four URXCLK clock cycles.
00
01
10
11
0 URXCLK cycle delay
7-6
7-6
early_RXENB_l[1:0]
1 URXCLK cycle delay
2 URXCLK cycle delay - standard operation
3 URXCLK cycle delay
Receive Enable interface line assertion for FIFO full
1
0
Enables RXENB to control flow for ingress FIFO full
RXENB interface line is not used for ingress link level flow control (typi-
cally IBFC mode)
5
5
RXENB_enb_l
4-3
4-3
Unused
Ingress PE data delay for correct resampling
Bit
0
1
Selected Clock
2
2
RXDATA_KEEPER
ShadowRxClockOut - switch loopback
ShadowRXclockIn - Normal operation
1-0
1-0
Unused
Converter Configuration Table Registers
Page 102 of 154
prssi.02.fm
March 1, 2001
IBM [ IBM ]
