IBM3229P2035
IBM Packet Routing Switch Serial Interface Converter
Advance
4.1.1.31 Switch X PLL Setting Register
These settings correspond to a VCO setting of 660 MHz. The PLL observe bits will automatically overwrite
what has been written by the microprocessor.
Unused
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Reset Output Status (Power-on-Reset)
Address in Word Mode
Address in Byte Mode
Access Type
‘0800 C000’
x'90’
x'90 to 93’
Read/Write
Bits /
Word
Bits /
Bytes
Name
Description
Programmable Switch X PLL multiplier.
31-28
7-4
PLL_SWX_MULT
0010
Normal operation, as the reference clock is 55 - 62.5 MHz for a switch byte
clock of 110 - 125 MHz.
27
26-24
23
3
PLL_SWX_OBSV
PLL_SWX_OBSV
PLL_SWX_OBSV
PLL_SWX_OBSV
PLL_SWX_OBSV
PLL_SWX_OBSV
Switch X PLL Observe Reset
2-0
7
Switch X PLL Observe: Multiplier bits 3-1.
Switch X PLL Observe: Multiplier bit 0
22-20
19-17
16
6-4
3-1
0
Switch X PLL Observe: buffered version of range B (2-0)
Switch X PLL Observe: buffered version of range A (2-0)
Switch X PLL Observe Reset (delayed by one clock)
1
0
Switch X PLL reset: equivalent to bypass mode
Normal operation after PLL programming
15
14
7
6
PLL_SWX_RESET
PLL_SWX_LOCK
1
0
Switch X PLL locked
PLL is unlocked
Programmable Switch X PLL Tune.
13-8
5-0
PLL_SWX_TUNE
010011 Normal operation as product of forward and feedback dividers is between
(6/4)<M<6
7-6
5-3
7-6
5-3
Unused
Programmable Switch X PLL Range B.
PLL_SWX_RANGB
PLL_SWX_RANGA
101
Programmable Switch X PLL Range A.
010 PLLOUTA frequency is 66 - 134 MHz
Normal operation as PLLOUTB frequency is 133 - 267 MHz
2-0
2-0
Converter Configuration Table Registers
Page 94 of 154
prssi.02.fm
March 1, 2001
IBM [ IBM ]
