IBM3229P2035
IBM Packet Routing Switch Serial Interface Converter
Advance
List of Figures
Figure 1: Overall Switch Subsystem Configuration ..................................................................... 14
Figure 2: IBM Packet Routing Switch Serial Interface General Data Flow .................................. 14
Figure 3: Converter Functional Block Diagram ............................................................................ 18
Figure 4: Bit and Byte Notation .................................................................................................... 19
Figure 5: Ingress Timing for RXENB Deasserted by Converter for 1 Clock Cycle ...................... 21
Figure 6: Ingress Timing for RXENB Deasserted by Converter for 3 Clock Cycles ..................... 22
Figure 7: Ingress Timing for RXPAV Deasserted by Protocol Engine for 1 Clock Cycle ............. 22
Figure 8: Ingress Timing for RXPAV Deasserted by Protocol Engine for 3 Clock Cycles ........... 23
Figure 9: Ingress Packets in Back-to-Back from Protocol Engine ............................................... 23
Figure 10: TXFULL Timing .......................................................................................................... 26
Figure 11: Egress Timing for Back-to-Back Packets ................................................................... 26
Figure 12: Example of Converter Ingress Idle Packet ................................................................. 30
Figure 13: Example of Converter Egress Idle Packet .................................................................. 32
Figure 14: IBM 28.4 Packet Routing Switch (switch) Packet Qualifier Bits Reshuffling ............... 34
Figure 15: Path Selection ............................................................................................................ 36
Figure 16: Converter Interface Lines ........................................................................................... 42
Figure 17: Configuration in Normal Operating Mode ................................................................... 43
Figure 18: Protocol Engine Loopback Through Path X or Path Y ............................................... 43
Figure 19: Protocol Engine External Loopback Through Path X ................................................. 44
Figure 20: Switch X Loopback ..................................................................................................... 45
Figure 21: Clocks Distribution Diagram ....................................................................................... 46
Figure 22: IBM Packet Routing Switch Serial Interface Converter Processor Interface Lines ..... 51
Figure 23: Processor Read Access in 32-bit Burst Mode ............................................................ 52
Figure 24: Processor Write Access in 32-bit Burst Mode ............................................................ 52
Figure 25: Processor Read Access in 8-bit Byte Mode ............................................................... 53
Figure 26: Processor Write Access in 8-bit Byte Mode ............................................................... 53
Figure 27: Register Mapping ....................................................................................................... 54
Figure 28: Register Addressing ................................................................................................... 54
Figure 29: DI and Data Aligned Serial Link (DASL) Startup Sequence Path X ........................... 64
Figure 30: Enabling of Data Aligned Serial Link (DASL) Data Transmission and Reception Path X
64
Figure 31: DI and Data Aligned Serial Link (DASL) Startup Sequence Path Y ........................... 71
Figure 32: Enabling of Data Aligned Serial Link (DASL) Data Transmission and Reception Path Y
71
Figure 33: Converter Latency Diagram ...................................................................................... 108
Figure 34: Detection of Line Card Fully Inserted ....................................................................... 115
Figure 35: VDDA Filtering .......................................................................................................... 117
List of Figures
prssi.02LOF.fm
March 1, 2001
Page 8 of 154
IBM [ IBM ]
