IBM3229P2035
Advance
IBM Packet Routing Switch Serial Interface Converter
4.1.1.14 Interrupt Enable _Y Register ........................................................................................ 76
4.1.1.15 DASL M3 Picocode X Register .................................................................................... 77
4.1.1.16 SDC Controller X Register (SDC_Debug_CNTL X) ..................................................... 78
4.1.1.17 SDC Data X in Bus Register (SDC_Debug_Data_In X) ............................................... 79
4.1.1.18 SDC Data X Out Bus Register (SDC_Data X_Out Bus) .............................................. 80
4.1.1.19 SDC Address X Bus Register (SDC_Debug_Data_Address X) ................................... 81
4.1.1.20 SDC Status X Register (SDC_Status_Reg X) .............................................................. 82
4.1.1.21 DASL M3 Picocode Y Register .................................................................................... 83
4.1.1.22 SDC Controller Y Register (SDC_Debug_CNTL Y) ..................................................... 84
4.1.1.23 SDC Y Data In Bus Register (SDC_Debug_Data_In Y) ............................................... 85
4.1.1.24 SDC Data Y Out Bus Register (SDC_Data Y_Out Bus) .............................................. 86
4.1.1.25 SDC Address Y Bus Register (SDC_Debug_Data_Address Y) ................................... 87
4.1.1.26 SDC Status Y Register (SDC_Status_Reg Y) .............................................................. 88
4.1.1.27 Event 2 Checker Enable_X and _Y Registers .............................................................. 89
4.1.1.28 Event 2 µP Interrupt Enable_X and _Y Registers ........................................................ 90
4.1.1.29 Event 2 _X and _Y Registers ....................................................................................... 91
4.1.1.30 ABIST Failure Test Status _X_Y Registers .................................................................. 93
4.1.1.31 Switch X PLL Setting Register ..................................................................................... 94
4.1.1.32 Switch Y PLL Setting Register ..................................................................................... 95
4.1.1.33 Chip ID Register ........................................................................................................... 96
4.1.1.34 Protocol Engine PLL Setting Register (PE PLL Register) ............................................ 97
4.1.1.35 Common Control Register ............................................................................................ 98
4.1.1.36 Interrupt Register Indirection ...................................................................................... 100
4.1.1.37 Ingress PE Settings Register (INGRESS_PE_INTERFACE (IPI) - Receive) ............. 101
4.1.1.38 Egress PE Setting Register (EGRESS_PE_INTERFACE - Transmit) ....................... 103
4.1.1.39 Common PE Setting Register (PE (Common)) .......................................................... 105
4.1.1.40 Parity and CRC Error Count Register (PARITY_Error_Count) .................................. 107
5. IBM Packet Routing Switch Serial Interface Converter Latency ........................ 108
6. JTAG Description .................................................................................................... 109
7. I/O Definition and Package Pin Assignment ........................................................ 111
7.1 Signals Description ..................................................................................................................... 111
7.2 I/O Timing ..................................................................................................................................... 124
7.2.1 IBM Packet Routing Switch Serial Interface Converter A.C. Characteristics ...................... 124
7.2.1.1 AC parameters characteristics ..................................................................................... 124
7.2.1.2 Protocol Engine (UTOPIA-3 like) Interface A.C. Specifications ................................... 124
7.2.1.3 Microprocessor Interface A.C. Specifications ............................................................... 125
8. Electrical Specifications ......................................................................................... 126
8.1 Power Sequencing ...................................................................................................................... 126
8.2 Recommended Operating Conditions ....................................................................................... 127
8.3 Signal Pin Assignments ............................................................................................................. 129
8.4 Power Signals .............................................................................................................................. 137
9. Packaging Information ........................................................................................... 140
prssi.02TOC.fm
March 1, 2001
Page 5 of 154
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