欢迎访问ic37.com |
会员登录 免费注册
发布采购

IBM3229P2035 参数 Datasheet PDF下载

IBM3229P2035图片预览
型号: IBM3229P2035
PDF下载: 下载PDF文件 查看货源
内容描述: [Packet Routing Switch, CMOS, CBGA360, 25 X 25 MM, CERAMIC, BGA-360]
分类和应用: 电信电信集成电路
文件页数/大小: 154 页 / 1172 K
品牌: IBM [ IBM ]
 浏览型号IBM3229P2035的Datasheet PDF文件第6页浏览型号IBM3229P2035的Datasheet PDF文件第7页浏览型号IBM3229P2035的Datasheet PDF文件第8页浏览型号IBM3229P2035的Datasheet PDF文件第9页浏览型号IBM3229P2035的Datasheet PDF文件第11页浏览型号IBM3229P2035的Datasheet PDF文件第12页浏览型号IBM3229P2035的Datasheet PDF文件第13页浏览型号IBM3229P2035的Datasheet PDF文件第14页  
IBM3229P2035  
IBM Packet Routing Switch Serial Interface Converter  
Advance  
List of Tables  
Table 1: Ingress I/O Pin Description ............................................................................................... 9  
Table 2: Egress I/O Pin Description .............................................................................................. 13  
Table 3: Output Port Bitmap Fields ............................................................................................... 17  
Table 4: Packet Qualifier for Ingress Idle Packet .......................................................................... 18  
Table 5: Packet Qualifier for Ingress Data Packet ........................................................................ 18  
Table 6: Packet Qualifier for Ingress Data Packet ........................................................................ 19  
Table 7: Packet Qualifier for Egress Idle Packet .......................................................................... 20  
Table 8: Packet Qualifier for Egress Data Packet ........................................................................ 21  
Table 9: Packet Qualifier for Egress Data Packet ........................................................................ 22  
Table 10: Output Queue Grant Bit Map Fields ............................................................................. 29  
Table 11: Selecting the Signal That Appears on the TO_SMOOTH_PLL_IN Signal .................... 34  
Table 12: External Clocks Description .......................................................................................... 35  
Table 13: Register Reset Settings ................................................................................................ 36  
Table 14: I/O Initialization Values ................................................................................................. 37  
Table 15: Path Resets .................................................................................................................. 37  
Table 16: System Mode PLL Resets ............................................................................................ 38  
Table 17: Supported JTAG Instructions ........................................................................................ 97  
Table 18: Compliance Pattern ...................................................................................................... 98  
Table 19: ID Code Description ...................................................................................................... 98  
Table 20: Tests Signals ................................................................................................................ 99  
Table 21: JTAG Interface External Signals ................................................................................. 100  
Table 22: Processor Interface Signals ........................................................................................ 101  
Table 23: IBM Packet Routing Switch Serial Interface Converter (the converter) Signals ......... 102  
Table 24: Receive PE Interface Signals ..................................................................................... 103  
Table 25: Transmit PE Interface Signals .................................................................................... 103  
Table 26: Clocking/PLL External Signals .................................................................................... 104  
Table 27: Back Pressure Serial Link Signals .............................................................................. 105  
Table 28: Miscellaneous External Signals .................................................................................. 106  
Table 29: Spares Signals Used to Carry Additional DC Voltages .............................................. 107  
Table 30: Debug Purpose External Signals ................................................................................ 107  
Table 31: DBG_SELECT Bus Definition ..................................................................................... 108  
Table 32: Absolute Maximum Ratings ........................................................................................ 114  
Table 33: LVCMOS Compatible I/Os .......................................................................................... 115  
Table 34: LVTTL Compatible I/Os .............................................................................................. 115  
Table 35: Recommended Operating Conditions for all I/Os ....................................................... 116  
Table 36: Power Dissipation ....................................................................................................... 116  
Table 37: Signal Pins Sorted by Grid Location ........................................................................... 117  
List of Tables  
prssi.02LOT.fm  
March 1, 2001  
Page 10 of 154  
 复制成功!