IBM3229P2035
Advance
IBM Packet Routing Switch Serial Interface Converter
Table 38: Signal Pins Sorted By Signal Name ............................................................................ 121
Table 39: Ground Signals ........................................................................................................... 125
Table 40: 2.5 V VDD Signals ....................................................................................................... 126
Table 41: 1.5 V South VDD 2 Signals ......................................................................................... 127
Table 42: 1.5 V East VDD 3 Signals ........................................................................................... 127
Table 43: 3.3 V North VDD 4 Signals ......................................................................................... 127
Table 44: 1.5 V West VDD 5 Signals .......................................................................................... 127
Table 45: Interface Description for DASL Internal Signals .......................................................... 130
Table 46: Debug Control Field Definitions .................................................................................. 134
Table 47: Status Register Definition ........................................................................................... 135
Table 48: Data Aligned Serial Link (DASL) Signals for Synchronization .................................... 135
Table 1: Ingress I/O Pin Description 21
Table 2: Egress I/O Pin Description 25
Table 3: Output Port Bitmap Fields 29
Table 4: Packet Qualifier for Ingress Idle Packet 30
Table 5: Packet Qualifier for Ingress Data Packet 30
Table 6: Packet Qualifier for Ingress Data Packet 31
Table 7: Packet Qualifier for Egress Idle Packet 32
Table 8: Packet Qualifier for Egress Data Packet 33
Table 9: Packet Qualifier for Egress Data Packet 34
Table 10: Output Queue Grant Bit Map Fields 41
Table 11: Selecting the Signal That Appears on the TO_SMOOTH_PLL_IN Signal 46
Table 12: External Clocks Description 47
Table 13: Register Reset Settings 48
Table 14: I/O Initialization Values 49
Table 15: Path Resets 49
Table 16: System Mode PLL Resets 50
Table 17: Supported JTAG Instructions 109
Table 18: Compliance Pattern 110
Table 19: ID Code Description 110
Table 20: Tests Signals 111
Table 21: JTAG Interface External Signals 112
Table 22: Processor Interface Signals 113
Table 23: IBM Packet Routing Switch Serial Interface Converter (the converter) Signals 114
Table 24: Receive PE Interface Signals 115
Table 25: Transmit PE Interface Signals 115
Table 26: Clocking/PLL External Signals 116
Table 27: Back Pressure Serial Link Signals 117
Table 28: Miscellaneous External Signals 118
Table 29: Spares Signals Used to Carry Additional DC Voltages 119
Table 30: Debug Purpose External Signals 119
Table 31: DBG_SELECT Bus Definition 120
prssi.02LOT.fm
March 1, 2001
List of Tables
Page 11 of 154
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