IBM3229P2035
IBM Packet Routing Switch Serial Interface Converter
Advance
3.6 Interfacing Data Aligned Serial Link (DASL) Macro ................................................................... 37
3.6.1 Ingress Data Aligned Serial Link (DASL) Interface ................................................................ 37
3.6.2 Functions ............................................................................................................................... 37
3.6.3 Packets Format ...................................................................................................................... 37
3.6.3.1 Idle Packets .................................................................................................................... 37
3.6.3.2 Idle Packet CRC Computing ........................................................................................... 37
3.6.3.3 Synchronization Packets Format .................................................................................... 38
3.6.3.4 Data Packets .................................................................................................................. 38
3.6.4 Egress Data Aligned Serial Link (DASL) Interface (EDI) ....................................................... 38
3.6.4.1 Packets Format .............................................................................................................. 40
3.6.4.2 Data Packets .................................................................................................................. 41
3.6.5 IBM 28.4G Packet Routing Switch (switch) in band Output Queue Grant Information .......... 41
3.6.6 IBM Packet Routing Switch Serial Interface Converter (the converter) Switch Interface ....... 42
3.7 Egress & Ingress Interface Diagnostic Functions ..................................................................... 42
3.7.1 Loopbacks .............................................................................................................................. 42
3.7.1.1 Normal Operating Mode ................................................................................................. 43
3.7.1.2 Protocol Engine X/Y Loopback ....................................................................................... 43
3.7.1.3 Protocol Engine (PE) External Loopback ....................................................................... 44
3.7.1.4 Switch X/Y Loopback ...................................................................................................... 44
3.8 Clocks Generator Description ...................................................................................................... 46
3.8.1 IBM Packet Routing Switch Serial Interface Converter Internal Clocks Description .............. 47
3.8.2 IBM Packet Routing Switch Serial Interface Converter External Traffic: ............................... 47
3.9 IBM Packet Routing Switch Serial Interface Converter RESET Scheme Description ............. 48
3.9.1 Reset Strategy ....................................................................................................................... 48
3.9.2 Power-On-Reset (POR) Procedure ....................................................................................... 48
3.9.3 Path Reset ............................................................................................................................. 49
3.9.4 PLL Reset .............................................................................................................................. 50
3.9.5 Ingress/Egress Interface Reset .............................................................................................. 50
3.10 Microprocessor Interface Description ....................................................................................... 50
3.10.1 The microprocessor interface: ............................................................................................. 50
3.10.2 Processor Interface Lines .................................................................................................... 51
3.10.3 Processor Interface I/O Lines Description ........................................................................... 51
3.10.4 32-Bit Mode Processor Interface Timing .............................................................................. 52
3.10.5 8-Bit Mode Processor Interface Timing ................................................................................ 53
4. Converter Configuration Table Registers ............................................................... 54
4.1 Error Detection, Reporting, and Interrupt Registers .................................................................. 55
4.1.1 Register Map .......................................................................................................................... 56
4.1.1.1 Setup 1_X PATH Register .............................................................................................. 57
4.1.1.2 Setup 2_X Path Register ................................................................................................ 58
4.1.1.3 Control _X PATH Register .............................................................................................. 59
4.1.1.4 X Plane Parity and CRC_Error_Count_X Registers ....................................................... 61
4.1.1.5 X Plane Events 1 Register (Event 1 _X) ......................................................................... 62
4.1.1.6 X Plane Event 1 Checker Enable Register (Event 1 Checker Enable_X ) ..................... 65
4.1.1.7 Interrupt Enable _X Register .......................................................................................... 66
4.1.1.8 Setup 1_Y PATH Register .............................................................................................. 67
4.1.1.9 Setup 2_Y PATH Registers ............................................................................................ 68
4.1.1.10 Control _Y PATH Registers .......................................................................................... 69
4.1.1.11 Y Plane Parity and CRC_Error_Count_Y Registers ..................................................... 72
4.1.1.12 Y Plane Events 1 Register (Event 1 _Y) ....................................................................... 73
4.1.1.13 Y Plane Event 1 Checker Enable Register (Event 1 Checker Enable _Y) ................... 75
prssi.02TOC.fm
March 1, 2001
Page 4 of 154
IBM [ IBM ]
