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IBM3229P2035 参数 Datasheet PDF下载

IBM3229P2035图片预览
型号: IBM3229P2035
PDF下载: 下载PDF文件 查看货源
内容描述: [Packet Routing Switch, CMOS, CBGA360, 25 X 25 MM, CERAMIC, BGA-360]
分类和应用: 电信电信集成电路
文件页数/大小: 154 页 / 1172 K
品牌: IBM [ IBM ]
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IBM3229P2035  
Advance  
IBM Packet Routing Switch Serial Interface Converter  
Figure 4: Bit and Byte Notation  
UTOPIA Level 3 Bit/Byte Notation  
MSB  
LSB  
7
7
0
7
0
7
0
0
7
Byte 0  
Byte 1  
Byte 2  
Byte 3  
IBM 28.4 G Packet Routing Switch/DASL Bit/Byte Notation  
MSB  
0
LSB  
7
0
0
7
0
7
Byte 0  
Byte 1  
Byte 2  
Byte 3  
The ingress block is the receive path between the protocol engine device (PE) and the rest of the converter  
logic. The egress block is the transmit path between the converter transmit logic and the PE.  
The timing on the UTOPIA-3 interface is the same for out of band flow control (OBFC) and for in band flow  
control (IBFC) modes except when operating in IBFC mode, the UTOPIA-3 flow control (RXENB at ingress  
and TXFULL at egress) is not normally used, as the packet header carries all the required information.  
However if a PE performs an interface level flow control (OBFC), those interface leads can be used for that  
purpose. In IBFC, fill-up (idle) packets flow through the interface to maintain a continuous stream of flow  
control information.  
3.1 Data Interface Between IBM Packet Routing Switch Serial Interface Converter and  
Protocol Engine  
UTOPIA-3 bit/byte notation is used throughout the protocol engine (PE) interface description. After the byte  
formatting (which reshuffles the byte position to match the IBM 28.4G Packet Routing Switch (switch) DASL  
interface), the switch DASL bit/byte notation is used.  
3.2 Functional Overview  
The IBM Packet Routing Switch Serial Interface Converter (the converter) ingress and egress interfaces are  
consistent with a subset of the UTOPIA-3 specifications:  
• Single PHY interface mode (connection between one converter and one protocol engine)  
Typical operating clock range is 100 - 111 MHz to match the IBM 28.4 G Packet Routing Switch clock rate  
(up to 111 MHz), but an interface clock rate as low as 50 MHz is supported  
• Only 32-bit data paths  
• Packet format is 64 - 80 bytes (programmed in the converter at configuration time)  
• Only packet level handshake mode (use of signals RXPAV in Receive Path and TXPAV in Transmit Path)  
prssi.02.fm  
Functional Description  
Page 19 of 154  
March 1, 2001  
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