IBM3229P2035
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IBM Packet Routing Switch Serial Interface Converter
Table 31: DBG_SELECT Bus Definition
Bits
Reg @8C 7-3
Bits
Description
Reg @8C 15-10
TxFraming in (from FIFO X)
Bits
15
Description
UTXCLK
14
SOP_to_TXfifo_x
Hold_toTXfifo_x
FAF_from_TXfifo-x
13
12
10111
10111
11
VALID_from_TXfifo_x
REQ_to_RXfifo_x
10
9-8
7-0
Unused
DATA_from_TXfifo_x [31:24] (8 bits master LU)
TxFraming in (from FIFO Y)
Bits
15
Description
UTXCLK
14
13
SOP_to_TXfifo_y
Hold_toTXfifo_y
11000’
11000’
12
FAF_from_TXfifo-y
VALID_from_TXfifo_y
REQ_to_RXfifo_y
Unused
11
10
9-8
7-0
DATA_from_TXfifo_y [31:24] (8 bits master LU)
TxFraming towards PE interface
Bits
15
14
13
12
Description
UTXCLK
Unused
11001’
11010’
11011’
11001’
11010’
11011’
HOLD_xfr_from_TXint
PENDING_from_TXframing
10-8 Unused??
7-0
DATA_from_TXframing [31:24] (8 bits master LU)
UTOPIA-3 like ingress interface
Bits
15
14
13
12
Description
URXCLK
RXSOP
RXFULL
RXENB
10-8 Unused
7-0
RXDATA [31:24] (8 bits master LU)
UTOPIA-3 like Egress interface
Bits
15
14
13
12
Description
UTXCLK
TXSOP
TXFULL
TXENB
10-8 Unused
7-0 TX DATA [31:24] (8 bits master LU)
prssi.02.fm
March 1, 2001
I/O Definition and Package Pin Assignment
Page 123 of 154
IBM [ IBM ]
