IBM3229P2035
Advance
IBM Packet Routing Switch Serial Interface Converter
Table 29: Spares Signals Used to Carry Additional DC Voltages
Input/Out-
Name
Level
Description
put
DDV1
DDV2
DNG1
DNG2
Input
Input
Input
Input
VDD1
VDD1
GND
Voltage I/O connected to VDD1 / 2.5 V
Voltage I/O connected to VDD2 / 2.5 V
Voltage I/O connected to GND
GND
Voltage I/O connected to GND
Table 30: Debug Purpose External Signals
Input/Out-
Name
Level
Description
put
AC_TEST_in
AC_TEST_out
Input
LVCMOS
LVCMOS
Test I/O used to determine the DASL macro propagation delay
Test I/O used to determine the DASL macro propagation delay
(based on 12 DASL delay lines)
Output
PE_PLLLOCK
SWITCH_X_PLLLOCK
SWITCH_Y_PLLLOCK
TEST_CLK
Output
Output
Output
Output
LVCMOS
LVCMOS
LVCMOS
LVCMOS
Test I/O used to determine the lock state of the PE PLL
Test I/O used to determine the lock state of the switch X PLL
Test I/O used to determine the lock state of the switch Y PLL
External oscillator clock input: 50 - 62.5 MHz
DBG_Bus
SELECT_0[15:0] and
DBG_Bus
2x 16 bit-buses provide direct I/O access (logic analyzer) to the
debug bus specified by the DBG_Select register @8C
Output
LVCMOS
SELECT_1[15:0]
prssi.02.fm
I/O Definition and Package Pin Assignment
Page 119 of 154
March 1, 2001
IBM [ IBM ]
