IBM3229P2035
Advance
IBM Packet Routing Switch Serial Interface Converter
The following drawing shows the flexibility in implementing the UTOPIA-3 like interface timing.
Figure 38: Options for Ingress UTOPIA-3 Like Interface Clocking
Nominal
Slow Process
Fast Process
ShadowRxClockOut
ShadowRXclockIn
0
1
XCV1000 PBGA560
D
C
Q
D
C
Q
1
0
Shadow
RX ClockIn
Clock Tree
Ingress
Used for Loop
180 ps
per inch
Must Have Equivalent
Delay Structure
Enable Shadow RX Clock Out_En
Shadow RXCLK Out
Reference
Point
Clock Tree
Egress
PLL
Clock
Source
PLL6SFLIBI
Enable RXCLK Out
Enable TXCLK Out
50 - 800 MHz
PE RXCLK Out
DLL
Q
D
C
PLL used as
Frequency Multiplier
Max IOB Clock to Output: 3.8 ns
Min IOB Clock to Output: 1 ns
Nominal Setup: 1 ns
Nominal Hold: 0 ns
Clock Skew: 0 - 300 ps
DLL Jitter: 120 - 280 ps
PE TXCLK Out
Q
D
C
IBM Packet Routing Switch Serial Interface Converter
7.2.1.3 Microprocessor Interface A.C. Specifications
Symbol
f
Parameter
Clock Frequency
Clock Period
Test Condition
Min
25
Typical
50
Max
Unit
MHz
ns
66
40
tck
15
20
tpw
Clock Pulse Width
Clock to Output valid
Input Set-up Time
Input Hold Time
High or Low
xx pF, all outputs
All inputs
ns
TcTOV
tsu
10
ns
2
0
ns
tHOLD
All inputs
ns
prssi.02.fm
March 1, 2001
I/O Definition and Package Pin Assignment
Page 125 of 154
IBM [ IBM ]
