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IBM3229P2035 参数 Datasheet PDF下载

IBM3229P2035图片预览
型号: IBM3229P2035
PDF下载: 下载PDF文件 查看货源
内容描述: [Packet Routing Switch, CMOS, CBGA360, 25 X 25 MM, CERAMIC, BGA-360]
分类和应用: 电信电信集成电路
文件页数/大小: 154 页 / 1172 K
品牌: IBM [ IBM ]
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IBM3229P2035  
IBM Packet Routing Switch Serial Interface Converter  
Advance  
8. Electrical Specifications  
Table 32: Absolute Maximum Ratings  
Parameter  
VDD  
Description  
Min  
-0.5  
-0.5  
-0.5  
Typ  
2.5  
Max  
2.7  
Units  
Supply voltage VDD  
Input voltage  
V
V
V
VIN  
VDD+0.6  
VDD+0.6  
VOUT  
Output voltage  
Thermal impedance junction to ambient package  
Airflow=0  
14.7  
13.3  
°C/W  
°C/W  
°C/W  
Thermal impedance junction to ambient package  
Airflow=100FPM  
Thermal impedance junction to ambient package  
Airflow=200FPM  
11.9  
1.9  
Thermal impedance junction to case package  
Storage temperature  
°C/W  
°C  
TS  
TA  
-65  
0
150  
125  
Operating junction temperature range  
Electrostatic discharge  
°C  
-3.000  
6,000  
3,000  
V
Note: Permanent device damage may occur if the above absolute maximum ratings are exceeded. Functional operation should be  
restricted to the conditions as detailed in the operational section of this data sheet. Exposure to absolute maximum rating conditions for  
extended periods may affect device reliability.  
8.1 Power Sequencing  
In order to prevent latchup (and destruction) of the chip, the power supplies must be sequenced up and down  
in a manner that any supply is greater than or equal to the voltage of another supply of lesser value both  
during "turn on" and "turn off" (including a quick toff - ton sequence).  
For example, 3.3 V >/= 2.5 >/= 1.5 V during power up and power down. Actually up to 400 mV of negative  
voltage can be tolerated during the sequence between any two supplies. There is no time delay requirement,  
only a negative voltage restriction. Ideally, all supplies would rise together until they reach their operating  
level and all would fall together until they reach zero.  
If one could design a 400 mV (max) diode and place it between 3.3 V (cathode) and 2.5 V (anode), and  
another between 2.5 V (cathode) and 1.5 V (anode), that would ensure that the 400mV diodes internal to the  
chip did not get forward biased more than the 400 mV, which would keep the chip out of latchup conditions.  
Also, the 3.3 V supply should not exceed the 2.5 V supply by more than 2.7 V during power up/down, and  
1.3V in constant use.  
Electrical Specifications  
Page 126 of 154  
prssi.02.fm  
March 1, 2001