IBM3009K2672
IBM SONET/SDH Framer
Transmit/Receive ATM/PPP Handler Features ................................................................................ 106
Utopia Levels 1 and 2 Block ATM Features ..................................................................................... 108
Utopia Level 2+ Block PPP Features ................................................................................................ 108
Transmit Telecom Bus Interface ....................................................................................................... 108
Receive Telecom Bus Interface ........................................................................................................ 109
Microprocessor Interface .................................................................................................................. 109
Boundary Scan Interface ................................................................................................................... 109
Memory Map ................................................................................................................. 110
Chiplet Address Map ......................................................................................................................... 110
Register Descriptions .................................................................................................. 111
GPPINT Architecture .......................................................................................................................... 111
GPPINT Address Map ........................................................................................................................ 113
Chiplet Reset Registers ..................................................................................................................... 116
Chiplet Interrupt Request and Mask Registers ............................................................................... 119
Handshaking Error Indication and Mask Registers ........................................................................ 121
Clock Monitor Status and Mask Registers ...................................................................................... 124
Clock Monitor Test Period Register ................................................................................................. 126
Watchdog Timer Period Register ..................................................................................................... 127
Local (GPPINT) Configuration Register ........................................................................................... 128
IBM Internal Use Register .................................................................................................................. 128
Static Configuration Registers ......................................................................................................... 129
Loopback Capabilities ....................................................................................................................... 131
GP Access Protection Address Map ................................................................................................ 152
GPP Handler Architecture ................................................................................................................. 153
General Register Structure for GPP Handlers ................................................................................. 153
ACI_Tx1 (IT1) Counters ..................................................................................................................... 155
ACI_Tx1 Chiplet Address Map .......................................................................................................... 155
ACI_Tx1 (IT1) Reset Register ............................................................................................................ 157
ACI_Tx1 Interrupt Request and Mask Registers ............................................................................. 158
ACI_Tx1 Configuration Registers ..................................................................................................... 159
ACI_Tx2 (IT2) Counters ..................................................................................................................... 160
ACI_Tx2 Chiplet Address Map .......................................................................................................... 160
ACI_Tx2 (IT2) Reset Register ............................................................................................................ 162
ACI_Tx2 Interrupt Request and Mask Registers ............................................................................. 163
ACI_Tx2 Configuration Register ....................................................................................................... 164
ACI_Rx1 (IR1) Counters ..................................................................................................................... 165
ACI_Rx1 Chiplet Address Map .......................................................................................................... 165
ACI_Rx1 (IR1) Reset Register ........................................................................................................... 167
ACI_Rx1 (IR1) Status Register .......................................................................................................... 167
ACI_Rx1 (IR1) Interrupt Request and Mask Registers .................................................................... 168
ACI_Rx1 Configuration Registers .................................................................................................... 169
ACI_Rx2 (IR2) Counters ..................................................................................................................... 171
ACI_Rx2 Chiplet Address Map .......................................................................................................... 171
ACI_Rx2 (IR2) Reset Register ........................................................................................................... 172
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