Data Sheet
PowerPC 970FX
Preliminary
The bus frequency multiplier ratio will usually indicate the desired PLL multiplier setting. Ratios of 3 (3:1, 6:1,
12:1) should always use PLLMULT=0 (low) for a PLL multiplier of 12. The desired core frequency should be
divided by 12 to determine the required input SYSCLK frequency. Ratios of 2 (2:1, 4:1, 8:1, 16:1) should
always use PLLMULT=1 (high) to multiply SYSCLK by 8.
Note: Using bus frequency ratios of 3:1, 6:1 or 12:1 with PLLMULT=1 or ratios of 8:1 or 16:1 with
PLLMULT=0 is not recommended. Internal clock synchronization delays may reduce performance.
After the correct BUS_CFG(0:2) and PLLMULT pin settings are determined, the required SYSCLK input
frequency can be determined. The selected SYSCLK input frequency should be within the
minimum/maximum frequencies specified in Table 3-9 on page 23.
5.2.2 PLL_RANGE Configuration
The PLL VCO configuration for the PowerPC 970FX, using the pins PLL_RANGE1 and PLL_RANGE0, is
shown in Table 5-2 on page 58.
Note: There is some overlap between the PLL_RANGE settings. The best performance will always be
obtained by setting the PLL_RANGE bits to run the core processor clock at the highest part of the
selected range.
Table 5-2. PowerPC 970FX PLL Configuration
PLL_RANGE(1:0) Settings
Range Name
Low
PLL_RANGE1
PLL_RANGE0
Frequency Range
1.0 GHz to 1.4 GHz range
1.2 GHz to 1.8 GHz range
1.6 GHz to 2.2 GHz range
Reserved
0
0
1
1
0
1
0
1
Medium
High
Reserved
Notes:
1. When setting the PLL_RANGE bits, processor operation should be preferenced in the higher portion of the processor frequency
range for selected range bits. For example, a 2.0 GHz processor should have the PLL_RANGE bit settings (10).
2. The PLL_MULT and PLL_RANGE(1:0) bits may be overwritten by JTAG commands and the BUS_CFG bits may be changed by
SCOM commands during the POR (power on reset) sequence. Refer to the POR Application Note for more details.
System Design Information
October 14, 2005
Page 58 of 74
IBM [ IBM ]
