欢迎访问ic37.com |
会员登录 免费注册
发布采购

IBM25PPC750L-GB500AD2R 参数 Datasheet PDF下载

IBM25PPC750L-GB500AD2R图片预览
型号: IBM25PPC750L-GB500AD2R
PDF下载: 下载PDF文件 查看货源
内容描述: [RISC Microprocessor, 32-Bit, 500MHz, CMOS, CBGA360,]
分类和应用: 外围集成电路
文件页数/大小: 54 页 / 1135 K
品牌: IBM [ IBM ]
 浏览型号IBM25PPC750L-GB500AD2R的Datasheet PDF文件第4页浏览型号IBM25PPC750L-GB500AD2R的Datasheet PDF文件第5页浏览型号IBM25PPC750L-GB500AD2R的Datasheet PDF文件第6页浏览型号IBM25PPC750L-GB500AD2R的Datasheet PDF文件第7页浏览型号IBM25PPC750L-GB500AD2R的Datasheet PDF文件第9页浏览型号IBM25PPC750L-GB500AD2R的Datasheet PDF文件第10页浏览型号IBM25PPC750L-GB500AD2R的Datasheet PDF文件第11页浏览型号IBM25PPC750L-GB500AD2R的Datasheet PDF文件第12页  
PowerPC 740 and PowerPC 750 Microprocessor  
CMOS 0.20 µm Copper Technology, PID-8p, PPC740L and PPC750L, dd3.2  
- 3 cycle latency, 1 cycle throughput, single-precision multiply-add.  
- 3 cycle latency, 1 cycle throughput, double-precision add.  
- 4 cycle latency, 2 cycle throughput, double-precision multiply-add.  
- Hardware support for divide.  
- Hardware support for denormalized numbers.  
- Time deterministic non-IEEE mode.  
• System unit  
- Executes CR logical instructions and miscellaneous system instructions.  
- Special register transfer instructions.  
• Cache structure  
- 32K, 32-byte line, 8-way set associative instruction cache.  
- 32K, 32-byte line, 8-way set associative data cache.  
- Single-cycle cache access.  
- Pseudo-LRU replacement.  
- Copy-back or write-through data cache (on a page per page basis).  
- Supports all PowerPC memory coherency modes.  
- Non-blocking instruction and data cache (one outstanding miss under hits).  
- No snooping of instruction cache.  
• Memory management unit  
- 128 entry, 2-way set associative instruction TLB.  
- 128 entry, 2-way set associative data TLB.  
- Hardware reload for TLB's.  
- 4 instruction BAT's and 4 data BATs.  
- Virtual memory support for up to 4 exabytes (252) virtual memory.  
- Real memory support for up to 4 gigabytes (232) of physical memory.  
• Level 2 (L2) cache interface (Not available on the 740)  
- Internal L2 cache controller and 4K-entry tags; external data SRAMs.  
- 256K, 512K, and 1 Mbyte 2-way set associative L2 cache support.  
- Copy-back or write-through data cache (on a page basis, or for all L2).  
- 64-byte (256K/512K) and 128-byte (l-Mbyte) sectored line size.  
- Supports flow-through (reg-buf) synchronous burst SRAMs, pipelined (reg-reg) synchronous burst  
SRAMs, and pipelined (reg-reg) late-write synchronous burst SRAMs with optional parity checking.  
- Supports Core-to-L2 frequency divisors of ÷1, ÷1.5, ÷2, ÷2.5, and ÷3. The 750 supports the L2 fre-  
quency range specified in Section “L2 Clock AC Specifications,” on page 20. For higher L2 frequen-  
cies, please contact ppcsupp@us.ibm.com.  
• Bus interface  
- Compatible with 60x processor interface.  
- 32-bit address bus with optional parity checking.  
- 64-bit data bus (can be operated in 32-bit data bus mode) with optional parity checking.  
- Bus-to-core frequency multipliers from 2x to 10x. See the ”PLL Configuration,” on page 40.  
9/6/2002  
Version 2.0  
Page8  
 复制成功!