PowerPC 740 and PowerPC 750 Microprocessor
CMOS 0.20 µm Copper Technology, PID-8p, PPC740L and PPC750L, dd3.2
Overview
The 750 is targeted for high performance, low power systems and supports the following power management
features: doze, nap, sleep, and dynamic power management. The 750 consists of a processor core and an
internal L2 Tag combined with a dedicated L2 cache interface and a 60x bus. The L2 cache is not available
with the 740.
Figure 1 shows a block diagram of the 750.
Figure 1. 750 Block Diagram
Control Unit
Instruction Fetch
Branch Unit
Completion
32K ICache
BHT /
BTIC
System
Dispatch
Unit
GPRs
FPRs
FXU2
LSU
FPU
FXU1
Rename
Buffers
Rename
Buffers
32K DCache
L2 Tags
L2 Cache
BIU
60X
BIU
9/6/2002
Version 2.0
Page6
IBM [ IBM ]
