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IBM25PPC750L-GB500AD2R 参数 Datasheet PDF下载

IBM25PPC750L-GB500AD2R图片预览
型号: IBM25PPC750L-GB500AD2R
PDF下载: 下载PDF文件 查看货源
内容描述: [RISC Microprocessor, 32-Bit, 500MHz, CMOS, CBGA360,]
分类和应用: 外围集成电路
文件页数/大小: 54 页 / 1135 K
品牌: IBM [ IBM ]
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PowerPC 740 and PowerPC 750 Microprocessor  
CMOS 0.20 µm Copper Technology, PID-8p, PPC740L and PPC750L, dd3.2  
Pinout Listing for the PowerPC 750 360 CBGA Package (cont.)  
Signal Name  
Pin Number  
Active  
High  
High  
Low  
I/O  
Output  
I/O  
TSIZ[0:2]  
TT[0:4]  
WT  
A9, B9, C9  
C10, D11, B12, C12, F11  
C3  
Output  
5
G8, G10, G12, J8, J10, J12, L8, L10, L12, N8, N10, N12  
K13  
VDD  
6
High  
Output  
VOLTDET  
Note:  
1. For dd3.x on the 750 only, AVDD is no longer connected to the BGA pin. AVDD is filtered on the module from VDD. The 740 dd3.2 does require AVDD  
.
2. BVSEL Function:  
a. Unconnected or Pulled to OVDD — L2OVDD = 3.3 V nominal  
b. Connected to HRESET — OVDD = 2.5 V nominal  
c. Connected to GND — OVDD = 1.8 V nominal  
If BVSEL or L2VSEL is connected to GND with a series resistor, the resistor value must be 10 or less.  
3. These are test signals for factory use only and must be pulled up to OVDD for normal operation. During normal operation, L2_TSTCLK can be connected  
to GND if required.  
4. These pins are reserved for potential future use as additional L2 address pins.  
5. OVDD inputs supply power to the I/O drivers and VDD inputs supply power to the processor core.  
6. Internally tied to L2OVDD in the 750 360 CBGA package. This is NOT a supply pin.  
PowerPC 750 Package  
Package Type  
Package outline  
Interconnects  
Ceramic Ball Grid Array (CBGA)  
25 x 25mm  
360 (19 x 19 ball array - 1)  
1.27mm (50mil)  
2.65mm  
Pitch  
Minimum module height  
Maximum module height  
Ball diameter  
3.20mm  
0.89mm (35mil)  
Page 35  
Version 2.0  
9/6/2002  
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